1.  SUBJECT INTRODUCTION

2. Lecturer : 1) Cik Nur Farhan Kahar Email: nurfarhan@unimap.edu.my 2) Dr. Mohd Najmuddin bin Mohd Hassan Email: najmuddin@unimap.edu.my 3) En. Muhamad Sani bin Mustafa Email: sani@unimap.edu.my

3. PLV: 1) En. Mohammad Nazri bin Md. Nor Email: nazri@unimap.edu.my 2) En. Mohd. Ridzuan bin Mohd. Nor Email: mohdridzuan@unimap.edu.my

4. Grading: Examination = 70% Test 1 = 10% Test 2 = 10% Final Exam = 50% Course work = 30% Mini project = 15% Laboratories = 10% Assignments / Quizzes = 5%

5. Main Text Book M. Morris Mano & Charles R. Kime, Logic and Computer Design Fundamentals, 3 rd Edition, Prentice Hall.

6. Other References: Floyd, Digital Fundamentals, Prentice Hall. Mano & Ciletti, Digital Design, 4 th Ed.

7. Teaching Plan

8. Important Dates Week 8 (5 – 9 Nov 2012)  Test 1 Week 13 (10 – 14 Dec 2012)  Test 2 Week 14 (17 – 21 Dec 2012)  Mini Project Viva

9. Mini Project Groups of 4 (max). Title can be your own, recommended to work towards the RPS i-project.  Please consult Lecturers or PLVs for clarification on project suitability. Will be asked to submit proposal.

10. Chapter 1 : Registers & Register Transfers  Registers, Micro-operations & Implementations  Counters, register cells, buses & serial operations  Counters  Register cell design  Multiplexer and bus-based transfers for multiple registers  Serial transfers & micro-operations OUTLINE

11. Chapter 2 : Sequencing & Control  State machine  Datapath & control  Algorithmic State Machine (ASM)  Hardwired control  Microprogrammed control OUTLINE

12. Chapter 3 : Memory Basics  Memory definitions  Random Access Memory (RAM)  Static RAM integrated circuits  Arrays of SRAM IC  Dynamic RAM IC  DRAM types  Arrays of DRAM IC OUTLINE

13. Chapter 4 : Computer Design Basics  Datapath ALU  Barrel Shifter  Control Word OUTLINE

14. Course Outcomes (COs) CO1: Ability to illustrate a digital system in Register Transfer Language (RTL) form. CO2: Ability to design sequential systems using Finite State Machine (FSM) and Algorithmic State Machine (ASM) CO3: Ability to design a digital system with control unit CO4: Ability to design and simulate using software tool and synthesize a digital design to FPGA device.

15. What to do BEFORE Lab … Download the lab sheet and relevant materials from portal / e-learning.

16. Altera Max+Plus II Altera UP-2 Training Board

17. THANK YOU