A 12-bit low-power ADC for SKIROC Laurent ROYER, Samuel MANEN, Pascal GAY LPC Clermont-Ferrand

ADC requirements for Si-W Ecal Consumption: For ADC, arbitrary limited to 10% of the VFE power budget) 2.5 µW/ch max. Power pulsing needed Resolution: 12 bits (with a 2-gain shaping) Time of conversion: Time budget of 500 µs to convert all data of all triggered channels Compactness The Si-W calo requires an efficient VFE electronics. This electronics has to process a 15-bit dynamic range signal with a minimal accuracy of 8 bits. The power budget is limited to 25 uW for each channel. We can then give the main requirements concerning the ADC, the last block of the read out electronics. The power consumption must not exceed 2.5uW, which is 10% of the total power budget of the channel. A power pulsing must be implemented. To cover the 15-bit dynamic range, a resolution of 10 bits is required if a 3 gain shaping is implemented, and a 12-bit ADC with a 2-gain shaping. The time to convert is imposed by the time budget of 500us to …. The die area must be as small as possible and in Skiroc chip the area of the analog par is about a quarter of a millimeter square . Analog electronics busy A/D conv. DAQ IDLE MODE 1ms (.5%) .5ms (.25%) .5ms (.25%) 198ms (99%) 2

Cyclic ADC well-adapted for a one-ADC-per-channel architecture With one-ADC-per-channel architecture:  Short analog sensitive wires from memory to ADC  A digital Data Bus far from sensitive analog signals  Only ADCs of triggered channels powered ON  Conversions of channels done in parallel In the final 64-channel VFE chip, we proposed to implement/use one ADC per channel. This architecture presentsseveral advantages: The integrity analog signals is preserved/saved thanks to short …, thanks to the implementation of a digital data instead of an analog one and the ADC clock could be switch off during … Moreover only ADC of triggered channel can be switched ON w/ this architecture, power is saved. Nevertheless, this architecture may present a large pedestal channel-to-channel dispersion but it could be take into account during calibration. Integrity of analog signals saved Power saved No "fast" ADC required  Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated 3

The 12-bit cyclic ADC Low cost technology: 0.35 µm CMOS Austriamicrosystems Clock frequency: 1MHz Resolution: 12 bits Supply voltage : 3.5V Power pulsing system implemented Digital process of the bits (1.5 bit/stage algorithm) done with an external FPGA 10 chips have been tested  Results in the Calice Internal Note CIN-14 4

Power pulsing measurement 1 µs for recovery time after swicth ON included Master current sources switched OFF 5

Power pulsing measurement Variation of consumption vs Duty cycle of power pulsing Relative Consumption ( in %) Duty cycle ( time ON / total time of one cycle in %) 6

Instability Unstable amplifier Stable amplifier The problem has been fixed  Common Mode FeedBack instability with process fluctuation Chip submitted in March 09 to test the improvement 7

Measurement of the Linearity INL<+/-1 LSB DNL<+/-1 LSB No missing code 8

Estimation of the Noise Code distribution (input 1V) Standard deviation = 0.84 LSB (420µV) 9

A Building Block for the next version Skiroc Clock generator Common Mode to Differential Interface Digital processing DC voltages supply 10

Summary Measured performance in accordance with Si-W ECAL VFE requirements Time conversion < 7µs Consumption < 0.6µW per channel (power pulsing included) 2.5% of the power budget of one VFE channel Linearity: DNL < +/1 LSB & INL < +/-1 LSB Noise standard deviation < 0.8 LSB Yield improved with the new design of the amplifier A 12-bit cyclic ADC, dedicated to Si-W ECAL of ILC ready to be implemented in the next Skiroc chip. 11