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Turning photons into bits in the cold

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Presentation on theme: "Turning photons into bits in the cold"— Presentation transcript:

1 Turning photons into bits in the cold
Integrated signal processing and A/D conversion in one focal plane mounted ASIC Turning photons into bits in the cold 1/12/2019 Armin Karcher (LBNL)

2 Overview What is the CRIC 2 chip ? Why did we build it ?
How does it work ? Multi slope integrator ADC Test results Linearity Noise Cross-talk Power consumption AC-coupling Cold performance Where we go from here Conclusion 1/12/2019 Armin Karcher (LBNL)

3 CRIC 2: 4 Channel CCD readout
Pre-Amp CDS Multi-slope 13 Bit ADC Logic I/O Voltage Reference 1/12/2019 Armin Karcher (LBNL)

4 Why did we build it? The CRIC 2 chip is part of a fully-integrated detector readout system for the proposed SNAP space telescope. Integrating many detectors on a passively cooled focal plane strongly favors local readout with a micro-power ASIC. 1/12/2019 Armin Karcher (LBNL)

5 Readout electronics goals
Low noise: Photometry: 2.8e rms Large dynamic range: 96dB from noise floor to 130ke well depth (16-bit) Readout frequency: kHz & 50kHz Radiation tolerant: 10 kRad ionization (well shielded) Low power: ≈ 200mJ/image/channel ≈ 10mW/channel Operation at 140K and 300K Allow normal operation at 140K and chip testing at room temperature Compact Robust, space qualified 1/12/2019 Armin Karcher (LBNL)

6 Signal Path Voltage Reference Auto Gain Multi Slope Pipeline ADC
1/12/2019 Armin Karcher (LBNL)

7 Multi Slope Integrator
1/12/2019 Armin Karcher (LBNL)

8 Multi Slope Integrator
>16 bits of dynamic range with 13 bit ADC Large signals are Poisson noise dominated Charge is conserved (no offset) Gain calibration at 3 points fully characterizes the system. 1/12/2019 Armin Karcher (LBNL)

9 ADC design Pipeline architecture Low power High resolution Compact
12 identical stages minimize layout effort All capacitor design is radiation tolerant 1/12/2019 Armin Karcher (LBNL)

10 Integral Nonlinearity
1/12/2019 Armin Karcher (LBNL)

11 Integral Nonlinearity
deviation from line fit Note: 1 LSB ≈ 1e- ≈ 3.5 mV 1/12/2019 Armin Karcher (LBNL)

12 Differential Nonlinearity
1/12/2019 Armin Karcher (LBNL)

13 Noise Gain 32: Multislope dominated noise
Less than 1 bit RMS ADC noise ! Gain 1 1/12/2019 Armin Karcher (LBNL)

14 Crosstalk Crosstalk of less than 2 ADU for a full-scale signal.
This is at the measurement limit of our system. 1/12/2019 Armin Karcher (LBNL)

15 Power consumption Bandgap Reference  0.86 mW
Reference Buffer  mW ADC  mW Preamp/Integrator  mW Total power less than 17 mW/channel 1/12/2019 Armin Karcher (LBNL)

16 AC Coupling Vref ClampR 200KW Chip input To CCD output stage On/off
amplifier On/off C=1uF Clamp Vref Clamp is on during start up (CCD power up) to charge C, off afterwards. During normal operation: ClampR is closed only during the CCD reset level integration. On/off is closed only during CCD reset and video level integration. 1/12/2019 Armin Karcher (LBNL)

17 AC Coupling performance
No observable change in gain - DC coupled: Gain = µV/ADU - AC coupled: Gain = µV/ADU No change in noise 1/12/2019 Armin Karcher (LBNL)

18 Voltage Reference Only 7mV variation in voltage during cooldown
1/12/2019 Armin Karcher (LBNL)

19 Cold Performance Noise at 298K: 2.23ADU Noise at 153K: 1.90ADU
Noise reduction of ~15% Gain increase of ~5% 1/12/2019 Armin Karcher (LBNL)

20 Outlook Integration of digital control and timing is in process. Look for the CRIC3 chip next spring. Radiation testing is planned for this summer. A clock driver and bias generator chip (CLIC) is being developed to create a fully integrated focal plane readout system. 1/12/2019 Armin Karcher (LBNL)

21 CLIC chip in development
0V, 80V adj (Vsub dc) -5V, +15V adj (V clk) -5V, +10V adj (TG clk) Power supply (4V?) -5V, +10V adj (H clk) CLIC 0V, +5V adj (Output gate dc) -8V, +8V adj (SW clk) -8V, 0V adj (Reset gate clk) -15V, 0V adj (Reset drain dc) Input clock -25V,0 DC adj (Output drain dc) Config. data -20V,0 DC (p+ guard dc) 3.3V/2.5V (Analog/Dig) CRIC dc 1/12/2019 Armin Karcher (LBNL)

22 Conclusion Linearity is ~3.5µV (1 ADU) RMS
6.5µV cold noise is well below system goal Excellent crosstalk: -95dB The CRIC2 CCD readout chip meets all design requirements! 1/12/2019 Armin Karcher (LBNL)


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