ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

Memory Random Access Memory (RAM) Read-Only Memory (ROM) Contrary to Serial Access Memory (e.g. Tape) Static Random Access Memory (SRAM) Data stored so long as Vdd is applied 6-transistors per cell Faster Differential Dynamic Random Access Memory (DRAM) Require periodic refresh Smaller (can be implemented with 1 or 3 transistor) Slower Single-Ended Can be read and written Typically, addressable at byte granularity Read-Only Memory (ROM)

Block Diagram of Memory N-bit Data Input (for Write) N K-bit address lines Memory Unit K Read/Write 2k words N-bit per word Chip Enable N N-bit Data Output (for Read) Example: 2MB memory, byte-addressable N = 8 (because of byte-addressability) K = 21 (1 word = 8-bit)

Static Random Access Memory (SRAM) Wordline (WL) BitLine BitLine Typically each bit is implemented with 6 transistors (6T SRAM Cell) During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1

Dynamic Random Access Memory (DRAM) Wordline (WL) Bitline 1-transistor DRAM cell During a write, put value on bitline and then set WL=1 During a read, precharge bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write)

Memory Description Capacity of a memory is described as # addresses x Word size Examples: Memory # of addr # of data lines # of addr lines # of total bytes 1M x 8 1,048,576 8 20 1 MB 2M x 4 2,097,152 4 21 1K x 4 1024 10 512 B 4M x 32 4,194,304 32 22 16 MB 16K x 64 16,384 64 14 128 KB

How to Address Memory 4x8 Memory 2-to-4 Decoder A0 1 2 A1 3 CS Chip 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0 1 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit CS Chip Select D7 D6 D5 D4 D3 D2 D1 D0

How to Address Memory 4x8 Memory 2-to-4 Decoder A0=1 1 2 A1=0 3 CS 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A0=1 1 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1=0 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit CS Chip Select=1 D7 D6 D5 D4 D3 D2 D1 D0 Access address = 0x1

Use 2 Decoders 8x4 Memory 2-to-4 Decoder Row A1 1 2 A2 3 CS 1 Chip 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 1 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A2 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit CS Tristate Buffer (read) D0 D1 D2 D3 Chip Select 1 CS 1-to-2 Decoder Column Decoder A0

Tristate Buffer Similar to Transmission Gate En Input Output En Input Output Output En Input Vdd CMOS circuit Similar to Transmission Gate Could amplify signal (in contrast to a TG) Typically used for signal traveling, e.g. bus

Bi-directional Bus using Tri-state Buffer (control data flow for read/write) A Input/Output B

Read/Write Memory 8x4 Memory A1 1 2-to-4 Row Decoder 2 A2 3 CS 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 1 2-to-4 Row Decoder 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A2 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit CS Rd/Wr = 0 D0 D1 D2 D3 1 Chip Select = 0 CS 1-to-2 Column Decoder A0

Read/Write Memory 8x4 Memory A1 1 2-to-4 Row Decoder 2 A2 3 CS 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A1 1 2-to-4 Row Decoder 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 2 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit A2 3 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit 1-bit CS Rd/Wr = 1 D0 D1 D2 D3 1 Chip Select = 1 CS 1-to-2 Column Decoder A0

Building Memory in Hierarchy Design a 1Mx8 using 1Mx4 memory chips D7 D6 D5 D4 A19 A18 1Mx4 R/W CS A17 A0 CS D3 D2 D1 D0 A19 A18 A17 A0 1Mx4 R/W CS

Building Memory in Hierarchy Design a 2Mx4 using 1Mx4 memory chips A19 A18 A17 A0 1Mx4 R/W CS D3 D2 D1 D0 Note that 1-to-2 decoder is the wire itself (or use an inverter) 1-to-2 Decoder CS 1 A20 A19 A18 A17 A0 1Mx4 R/W CS

Building Memory in Hierarchy Design a 2Mx8 using 1Mx4 memory chips A19 A18 A17 A0 1Mx4 CS R/W D7 D6 D5 D4 D3 D2 D1 D0 A20 1-to-2 Decoder CS 1

Memory Model 32-bit address space can address up to 4GB (232) different memory locations Flat Memory Model 0x0A 0xB6 0x41 0xFC Lower Memory Address 0x00000000 Higher 0x00000001 0x00000002 0x00000003 0xFFFFFFFF 0x0D

Endianness [Danny Cohen 91] Byte ordering  How a multiple byte data word stored in memory Endianness (from Gulliver’s Travels) Big Endian Most significant byte of a multi-byte word is stored at the lowest memory address e.g. Sun Sparc, PowerPC Little Endian Least significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86 Some embedded & DSP processors would support both for interoperability

Endianness Examples Store 0x87654321 at address 0x0000, byte-addressable Lower Memory Address Lower Memory Address 0x0000 0x87 0x0000 0x21 0x0001 0x65 0x0001 0x43 0x0002 0x43 0x0002 0x65 0x0003 0x21 0x0003 0x87 Higher Memory Address Higher Memory Address BIG ENDIAN LITTLE ENDIAN

Memory Allocation (Little Endian) .data .globl declare declare: .align 0 .word 511 .byte 14 .align 2 .byte 14 .word 0x0B1E8143 .ascii “GAece” .half 10 .word 0x2B1E8145 .space 1 .byte 52 .align 1 .byte 16 .space 2 .byte 67 0xFF e ------ 0x34 1c 0x01 1 f ------ 1d ------ 0x00 0x47 0x10 2 10 1e 3 0x00 11 0x41 1f 4 0x0E 0x65 12 20 ------ 13 0x63 0x43 5 21 6 ------ 0x65 14 .align N: Align next datum on a 2n byte boundary .align 0: turn off automatic alignment for .half, .word, .float, and .double till the next .data directive .word: 4 bytes .half: 2 bytes .byte: 1 byte .space: 1-byte space .ascii: ASCII code (American Standard Code for Information Interchange) ------ 15 0x0A 7 0x0E 8 16 0x00 0x43 0x45 9 17 a 0x81 18 0x81 b 0x1E 0x1E 19 0x0B 0x2B c 1a d ------ 1b

Read Only Memory (ROM) “Permanent” binary information is stored Non-volatile memory Power off does not erase information stored ROM K-bit address lines N-bit Data Output 2k words N-bit per work K N

32x8 ROM 32x8 ROM 5 8 Each represents 32 wires A4 A3 5-to-32 Decoder A4 1 A3 2 5-to-32 Decoder 3 A2 A1 28 A0 29 30 31 Fuse can be implemented as a diode or a pass transistor D7 D6 D5 D4 D3 D2 D1 D0

Programming the 32x8 ROM D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 1 … 1 2 29 30 31 D7 D6 D5 D4 D3 D2 D1 D0 A4 A3 A2 A1 A0 5-to-32 Decoder

Example: Lookup Table Design a square lookup table for F(X) = X2 using ROM X F(X)=X2 1 2 4 3 9 16 5 25 6 36 7 49 X F(X)=X2 000 000000 001 000001 010 000100 011 001001 100 010000 101 011001 110 100100 111 110001

Square Lookup Table using ROM 1 X F(X)=X2 000 000000 001 000001 010 000100 011 001001 100 010000 101 011001 110 100100 111 110001 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 F5 F4 F3 F2 F1 F0

Square Lookup Table using ROM 1 X F(X)=X2 000 000000 001 000001 010 000100 011 001001 100 010000 101 011001 110 100100 111 110001 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 Not Used = X0 F5 F4 F3 F2 F1 F0

Square Lookup Table using ROM 1 X F(X)=X2 000 000000 001 000001 010 000100 011 001001 100 010000 101 011001 110 100100 111 110001 X2 3-to-8 Decoder 2 3 X1 4 X0 5 6 7 F5 F4 F3 F2 F1 F0

Classifying Three Basic PLDs Fixed AND plane (decoder) Programmable OR plane Connections (Programmable) Read-Only Memory (ROM) INPUT OUTPUT Programmable OR plane Connections Programmable Logic Array (PLA) AND plane INPUT OUTPUT Programmable AND plane Fixed OR plane Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers INPUT OUTPUT F/F

Programmable Logic Array (PLA) OR Plane B C Programmable AND Plane C C B B A A F2

Example using PLA

Example using PLA A B C AB AC BC A B C C C B B A A F1 F2

PAL Device A A B B IO1 IO2 IO1 IO1 IO1 Programmable AND Plane A IO2 B Fixed OR Plane

PAL Device Design Example B B C C D D IO1 IO1 IO1 Not programmed A IO2 B

CPLD and FPGA [Brown&Rose 96] Complex Programmable Logic Device (CPLD) Multiple PLDs (e.g. PALs, PLAs) with programmable interconnection structure Pioneered by Altera Field-Programmable Gate Array (FPGA) High logic capacity with large distributed interconnection structure Logic capacity  number of 2-input NAND gates Offers more narrow logic resources CPLD offers logic resources w/ a wide number of inputs (AND planes) Offer a higher ratio of Flip-flops to logic resources than CPLD HCPLD (High Capacity PLD) is often used to refer to both CPLD and FPGA

CPLD structure Logic block PLD PLD PLD PLD I/O block PLD PLD PLD PLD Interconnects

FPGA Structure Logic block I/O block Interconnects

FPGA Programmability Floating gate transistor Used in EPROM and EEPROM SRAM-controlled switch  Control Pass transistors Multiplexers (to determine how to route inputs) Antifuse Similar to fuse Originally an Open-Circuit One-Time Programmable (OTP)