1. ECE2030 Introduction to Computer Engineering Lecture 17: Memory and Programmable Logic Prof. Hsien-Hsin Sean Lee School of Electrical and Computer Engineering Georgia Tech

2. 2 Memory Random Access Memory (RAM) –Contrary to Serial Access Memory (e.g. Tape) –Static Random Access Memory (SRAM) Data stored so long as Vdd is applied 6-transistors per cell Faster Differential –Dynamic Random Access Memory (DRAM) Require periodic refresh Smaller (can be implemented with 1 or 3 transistor) Slower Single-Ended –Can be read and written –Typically, addressable at byte granularity Read-Only Memory (ROM)

3. 3 Block Diagram of Memory Example: 2MB memory, byte-addressable –N = 8 (because of byte-addressability) –K = 21 (1 word = 8-bit) 2 k words N-bit per word Memory Unit N-bit Data Input (for Write) N-bit Data Output (for Read) K-bit address lines Read/Write Chip Enable N N K

4. 4 Static Random Access Memory (SRAM) Typically each bit is implemented with 6 transistors (6T SRAM Cell) During read, the bitline and its inverse are precharged to Vdd (1) before set WL=1 During write, put the value on Bitline and its inverse on Bitline_bar before set WL=1 BitLine Wordline (WL)

5. 5 Dynamic Random Access Memory (DRAM) 1-transistor DRAM cell During a write, put value on bitline and then set WL=1 During a read, precharge bitline to Vdd (1) before assert WL to 1 Storage decays, thus requires periodic refreshing (read-sense-write) Bitline Wordline (WL)

6. 6 Memory Description Capacity of a memory is described as –# addresses x Word size –Examples: Memory# of addr# of data lines# of addr lines# of total bytes 1M x 81,048,5768201 MB 2M x 42,097,1524211 MB 1K x 41024410512 B 4M x 324,194,304322216 MB 16K x 6416,3846414128 KB

7. 7 How to Address Memory 1-bit 0 1 2 3 D7 D6 D5 D4 D3 D2 D1 D0 4x8 Memory 2-to-4Decoder A0 A1 CS Chip Select

8. 8 How to Address Memory 1-bit 0 1 2 3 D7 D6 D5 D4 D3 D2 D1 D0 4x8 Memory 2-to-4Decoder A0=1 A1=0 Access address = 0x1 CS Chip Select=1

9. 9 Use 2 Decoders 1-bit 0 1 2 3 8x4 Memory 2-to-4DecoderRowDecoder A1 A2 1-to-2 Decoder Column Decoder D0 D1 D2 D3 Tristate Buffer (read) 01 A0 CS Chip Select CS

10. 10 Tristate Buffer Similar to Transmission Gate Could amplify signal (in contrast to a TG) Typically used for signal traveling, e.g. bus InputOutput En Input Output En Output En Input Vdd CMOS circuit

11. 11 Bi-directional Bus using Tri-state Buffer Direction (control data flow for read/write) A B Input/Output

12. 12 Read/Write Memory 1-bit 0 1 2 3 8x4 Memory 2-to-4RowDecoder A1 A2 1-to-2 Column Decoder D0 D1 D2 D3 01 A0 CS Chip Select = 0 CS Rd/Wr = 0

13. 13 Read/Write Memory 1-bit 0 1 2 3 8x4 Memory 2-to-4RowDecoder A1 A2 1-to-2 Column Decoder D0 D1 D2 D3 01 A0 CS Chip Select = 1 CS Rd/Wr = 1

14. 14 Building Memory in Hierarchy Design a 1Mx8 using 1Mx4 memory chips D3 D2 D1 D0 A19 A18 A17 A0 1Mx4 R/W CS D7 D6 D5 D4 A19 A18 1Mx4 R/W CS A17 A0 CS

15. 15 Building Memory in Hierarchy Design a 2Mx4 using 1Mx4 memory chips A19 A18 A17 A0 1Mx4 R/W CS A19 A18 A17 A0 1Mx4 R/W CS A20 1-to-2 Decoder CS 1 0 D3 D2 D1 D0 Note that 1-to-2 decoder is the wire itself (or use an inverter)

16. 16 Building Memory in Hierarchy Design a 2Mx8 using 1Mx4 memory chips A19 A18 A17 A0 1Mx4 CSR/W A19 A18 A17 A0 1Mx4 CSR/W A19 A18 A17 A0 1Mx4 CSR/W A19 A18 A17 A0 1Mx4 CSR/W D7 D6 D5 D4 D3 D2 D1 D0 A19 A18 A17 A0 A20 1-to-2 Decoder CS 1 0

17. 17 Memory Model 32-bit address space can address up to 4GB (2 32 ) different memory locations Flat Memory Model 0x0A 0xB6 0x41 0xFC Lower Memory Address 0x00000000 Higher Memory Address 0x00000001 0x00000002 0x00000003 0xFFFFFFFF 0x0D

18. 18 [Danny Cohen 91] Endianness [Danny Cohen 91] Byte ordering  How a multiple byte data word stored in memory Endianness (from Gulliver’s Travels) –Big Endian MostlowestMost significant byte of a multi-byte word is stored at the lowest memory address e.g. Sun Sparc, PowerPC –Little Endian LeastlowestLeast significant byte of a multi-byte word is stored at the lowest memory address e.g. Intel x86 Some embedded & DSP processors would support both for interoperability

19. 19 Endianness Examples Store 0x87654321 at address 0x0000, byte-addressable 0x87 0x65 0x43 0x21 Lower Memory Address Higher Memory Address 0x0000 0x0001 0x0002 0x0003 BIG ENDIAN 0x21 0x43 0x65 0x87 Lower Memory Address Higher Memory Address 0x0000 0x0001 0x0002 0x0003 LITTLEENDIAN

20. 20 Memory Allocation (Little Endian).data.globl declare declare:.align 0.word 511.byte 14.align 2.byte 14.word 0x0B1E8143.align 2.ascii “GAece”.half 10.word 0x2B1E8145.space 1.byte 52.align 1.byte 16.space 2.byte 67 0xFF 0x01 0x00 0x0E ------ 0 1 2 3 4 5 6 0x0E 0x43 0x81 0x1E 0x0B ------ 7 8 9 a b c d 0x41 e f 10 11 0x47 0x63 12 13 0x65 0x0A 14 15 0x65 0x81 17 18 0x45 0x2B 19 1a 0x1E 0x00 16 1b ------ 1c 1d 0x34 1f 20 21 0x43 0x10 1e.align N.align N: Align next datum on a 2 n byte boundary.align 0.align 0: turn off automatic alignment for.half,.word,.float, and.double till the next.data directive.word.word: 4 bytes.half.half: 2 bytes.byte.byte: 1 byte.space.space: 1-byte space.ascii.ascii: ASCII code (American Standard Code for Information Interchange)

21. 21 Read Only Memory (ROM) “Permanent” binary information is stored Non-volatile memory –Power off does not erase information stored 2 k words N-bit per work ROM N-bit Data Output K-bit address lines N K

22. 22 32x8 ROM 85 0 1 2 3 28 29 30 31 D7D6D5D4D3D2 D1D0 A4 A3 A2 A1 A0 5-to-32 Decoder Each represents 32 wires Fuse can be implemented as a diode or a pass transistor

23. 23 Programming the 32x8 ROM A4A3A2A1A0D7D6D5D4D3D2D1D0 0000011000101 0000110001011 0001010110000 ………………………………… 1110100010000 1111001010110 1111111100001 0 1 2 29 30 31 D7D6D5D4D3D2 D1 D0 A4 A3 A2 A1 A0 5-to-32 Decoder

24. 24 Example: Lookup Table F(X) = X 2Design a square lookup table for F(X) = X 2 using ROM XF(X)=X 2 00 11 24 39 416 525 636 749 XF(X)=X 2 000000000 001000001 010000100 011001001 100010000 101011001 110100100 111110001

25. 25 Square Lookup Table using ROM XF(X)=X 2 000000000 001000001 010000100 011001001 100010000 101011001 110100100 111110001 0 1 2 3 F5F4F3F2 F1F0 X2 X1 X0 3-to-8 Decoder 4 5 6 7

26. 26 Square Lookup Table using ROM XF(X)=X 2 000000000 001000001 010000100 011001001 100010000 101011001 110100100 111110001 = X0 Not Used 0 1 2 3 F5F4F3F2 F1F0 X2 X1 X0 3-to-8 Decoder 4 5 6 7

27. 27 Square Lookup Table using ROM XF(X)=X 2 000000000 001000001 010000100 011001001 100010000 101011001 110100100 111110001 0 1 2 3 F5F4F3F2 F0 X2 X1 X0 3-to-8 Decoder 4 5 6 7 F1

28. 28 Classifying Three Basic PLDs Fixed AND plane (decoder)Programmable OR plane Programmable Connections (Programmable) Read-Only Memory (ROM) INPUT OUTPUT Programmable OR plane Programmable Connections Programmable Logic Array (PLA) Programmable AND plane INPUTOUTPUT Programmable AND plane Fixed OR plane Programmable Array Logic (PAL) Devices PAL: trademark of AMD, use PAL as an adjective or expect to receive a letter from AMD’s lawyers INPUT OUTPUT F/F

29. 29 Programmable Logic Array (PLA) C B A CCBBAA F2 Programmable AND Plane Programmable OR Plane

30. 30 PLA Example using PLA

31. 31 PLA Example using PLA C B A CCBBAA AB AC BC A B C F2 F1

32. 32 PAL Device A B IO1 IO2 IO1 BBAA IO2 Programmable AND Plane Fixed OR Plane

33. 33 PAL Device Design Example A B IO1 IO2 IO1 BBAADDCC Not programmed

34. 34 CPLD and FPGA [Brown&Rose 96] CPLDComplex Programmable Logic Device (CPLD) –Multiple PLDs (e.g. PALs, PLAs) with programmable interconnection structure –Pioneered by Altera FPGAField-Programmable Gate Array (FPGA) –High logic capacity with large distributed interconnection structure Logic capacity  number of 2-input NAND gates –Offers more narrow logic resources CPLD offers logic resources w/ a wide number of inputs (AND planes) –Offer a higher ratio of Flip-flops to logic resources than CPLD HCPLDHCPLD (High Capacity PLD) is often used to refer to both CPLD and FPGA

35. 35 CPLD structure PLD Logic block Interconnects I/O block

36. 36 FPGA Structure Logic block I/O block Interconnects

37. 37 FPGA Programmability Floating gate transistor –Used in EPROM and EEPROM SRAM-controlled switch  Control –Pass transistors –Multiplexers (to determine how to route inputs) Antifuse –Similar to fuse –Originally an Open-Circuit –One-Time Programmable (OTP)