1. Chapter 7 Memory and Programmable Logic

2. 7-1 Introduction Memory ROM is a programmable logic device(PLD)
RAM(random access memory): read and write operation
ROM(read only memory) : only read operation
ROM is a programmable logic device(PLD)
Other such units
PLA (Programmable Logic Array)
PAL (Programmable Array Logic)
FPGA(Field Programmable Gate Array)

3. Figure 7-1
A typical programmable logic device may have hundreds to millions of gates interconnected through hundreds to thousands of internal paths.

4. 7-2 Random-Access Memory
Words
Binary information in groups of bits
A word may represent a number, an instruction, one or more alphanumeric characters, or any other binary-coded information.
Bytes
A group of eight bits.
Capacity of a memory unit
The total number of bytes that it can store

5. Block Diagram of a Memory Unit
Address: identification number of each word
210: K(Kilo)
220: M(Mega)
230: G(Giga)
240: T(Tera)
250: P(Peta)

6. Block Diagram of a Memory Unit
Lines
Address lines (address bus)
Data lines (data bus)
Control lines (control bus)
The address lines select one particular word.
A decoder in the memory accepts this address and opens the paths needed to select the word specified.

7. A 1024 X 16 Memory Word size: 16 bits Address: from 0 to 1023

8. Write and Read Operations
Write operation
Transfer the binary address of the desired word to the address lines
Transfer the data bits that must be stored in memory to the data input lines.
Activate the write input
Read operation
Transfer the binary address of the desired word to the address lines
Activate the read input

9. Control inputs

10. HDL Example 7-1
// Read and write operations of memory. Memory size is 64 words of 4 bits each.
module memory (Enable, ReadWrite, Address, DataIn, DataOut);
input Enable, ReadWrite, [3:0] DataIn, [5:0] Address;
output [3:0] DataOut;
reg [3:0] DataOut;
reg [3:0] Mem [0:63];
(Enable or ReadWrite)
if (Enable)
if (ReadWrite)
DataOut = Mem[Address];
else
Mem[Address]= DataIn;
else DataOut = 4 ‘bz;
endmodule

11. Timing Waveforms
Access time: time required to select a word and read it.
Cycle time: time required to complete a write operation
Assume that a CPU operates with a clock frequency of 50 MHz.
The period for 1 cycle = 20 ns
Assume that its access time and cycle time do not exceed 50 ns

12. Types of Memories
Random access Memory -each word occupy one particular location.the access time is always the same
Sequential access Memory-information is read out only when the required word has been reached. the access time is variable.
Volatile -Memory units lose the stored information when power is turned off.
Nonvolatile-A nonvolatile memory retains its stored information after removal of power. ex) magnetic disk ,ROM(Read Only Memory)
Static RAM-The stored information remains valid as long as power is applied to the unit. Static RAM is easier to use and has shorter read and write cycles.
Dynamic RAM-The capacitors must be periodically recharged by refreshing the dynamic memory. Dynamic RAM offers reduced power consumption and larger storage capacity

13. 7-3 Memory Decoding Decoding circuit
To select the memory word specified by input address

14. Memory Cell
The equivalent logic of a binary cell that stores one bit of information
The binary cell stores one bit in its internal flip-flop
It has three inputs and one output. The read/write input determines the cell operation when it is selected.

15. Logical Construction of 4 x 4 RAM

16. Internal Construction
It has 16 binary cells
Memory enable=0; all outputs of the decoder =0 , none of the memory words are selected.
Memory enable=1; one of the four words is selected. The read/write input determines the operation.
During the read operation, the four bits of the selected word go through OR gates to the output terminals.
During the write operation, the data available in the input lines are transferred into the four binary cells of the selected word.

17. Coincident Decoding
The basic idea in two-dimensional decoding is to arrange the memory cells in an array that is close as possible as square. In this configuration, two k/2-input decoders are used instead of one k-input decoder.
In the two-decoder case,we need 64 AND gates with five inputs in each.
If the word address is (=40410), X=01100 (1210) and Y=10100(2010).

18. DRAM The DRAM cells consist of a MOS transistor and a capacitor.
They must be periodically recharged by refreshing the memory.
Most of DRAMs have a 1-bit word size, so several chips have to be combined to produce a larger word size.

19. Address Multiplexing
To reduce the number of pins in the IC package, designers utilize address multiplexing whereby one set of address input pins accommodates the address components.
Since the same set of pins is used for both parts of the address, the size of the package is decreased significantly.

20. 7-4 ERROR DETECTION AND CORRECTION
The reliability of a memory unit may be improved by error-detecting and correcting codes.
The post popular error-detecting code is the parity code.
An error correcting code generates multiple parity check bits which are stored with the data word in memory.
A syndrome is used to identify the bit in error.
If the specific bit in error is identified, then the error can be corrected by complementing the erroneous bit.

21. Hamming code
In Hamming code, k parity bits are to an n-bit data word, forming a new word of n + k bits.
The bit position are numbered in sequence from 1 to n+k.
Those positions numbered as a power of 2 are reserved for the parity bits.
The remaining bits are the data.

22. Hamming code for 8-bit words
The 8-bit data word :
Bit position:
P1 P P P
Where, P1 = XOR of bits (3,5,7,9,11) = 1  1  0  0  0 = 0
P2 = XOR of bits (3,6,7,10,11)= 1  0  0  1  0 = 0
P4 = XOR of bits (5,6,7,12) = 1  0  0  = 1
P8 = XOR of bits (9,10,11,12) = 0  1  0  = 1
Result 

23. Hamming code for 8-bit words
4-bit check bits:
C1 = XOR of bits (1,3,5,7,9,11)
C2 = XOR of bits (2,3,6,7,10,11)
C4 = XOR of bits (4,5,6,7,12)
C8 = XOR of bits (8,9,10,11,12)
A 0 check bit designates an even parity over the checked bits.
A 1 check bit designates an odd parity over the checked bits.

24. Error detection cases
Since the bits were stored with even parity C=C8C4C2C1=0000 (No error)
Bit position
No error
Error in bit 1
Error in bit 5
Check bits C8 C4 C2 C1
With error in bit 1 :
With error in bit 5:
The error can be corrected by complementing the corresponding bit.

25. Hamming code for data word of any length

26. Single-Error Correction , Double-Error Detection
The Hamming code can detect and correct only a single error. Multiple errors are not detected.
To correct a single error and detect double errors ,we include the additional parity bit, P13.
P13 is evaluated from the XOR of other 12 bits.
If C=0 and P=0 No error occurred
If C=1 and P=1 A single error occurred , which can be corrected
If C=1 and P=0 A double error occurred, which is detected but cannot be corrected
If C=0 and P=1 An error occurred in the P13 bit

27. 7-5 READ-ONLY MEMORY ROM block Diagram Internal logic of ROM
Combinational Circuit Implementation
Types of ROMs
Combinational PLDs

28. ROM Block Diagram ROM = Decoder + OR gates
k input lines(address)  2K word
The number of output lines n= the number of bits per word

29. 32 x 8 internal connections
Internal Logic of 32 x 8 ROM
32 words
1 word = 8-bit ( 8 OR gates)
32 x 8 internal connections

30. An Example of a ROM Truth Table(Partial)

31. Combinational Circuit Implementation
‘1’
‘0’
A7(I4,I3,I2 I1,I0) = (0,2,3,…,29)
Input 00011(3)
Output 

32. EXAMPLE 7-1
A0=B0

33. Types of ROMs PROM- irreversible and permanent
For large quantities, mask programming is economical .
For small quantities , programmable read-only memory(PROM) is more economical.(all ‘1’s)
PROM- irreversible and permanent
EPROM(Erasable PROM)- can be restructured to the initial value(UV light->discharge)
EEPROM(Electrically erasable PROM)- can be erased with electrical signals instead ultra violet light.

34. Combinational PLDs
A combinational PLD is an IC with programmable gates divided into an AND array and an OR array to provide an AND-OR sum of product implementation.
Three major types PLDs
(a) Fixed AND array + Programmable OR array
(b) Programmable AND array + Fixed OR array
(c) Programmable AND array + Programmable OR array

35. 7-6 PROGRAMMABLE LOGIC ARRAY
The PLA is similar to the PROM in the concept except that the PLA does not provide full decoding of the variables and does not generate all minterms.

36. PLA with 3 Inputs and 4 Product Terms, and 2 Outputs
Programmable OR array
Programmable AND array

37. Number of Programmed Fuses
The PLA consists of n inputs ,m outputs , k product terms(AND gate) ,and m sum terms(OR gate)
The number of programmed fuses is
, whereas that of a ROM is
F1=AB’ + AC + A’BC’
F2= (AC + BC)’

38. Implement the following two Boolean functions with a PLA
EXAMPLE 7-2
Implement the following two Boolean functions with a PLA
F1(A,B,C) =  (0,1,2,4)
F2(A,B,C) =  (0,5,6,7)

40. 7-7 PROGRAMMABLE ARRAY LOGIC
PAL: a programming logic device with a fixed OR array and a programmable AND array.
Not as flexible as the PLA
A typical PAL IC contains 8 inputs, 8 output, and eight sections, each consists of an eight-wide AND-OR array.

41. PAL with 4 inputs, 4 outputs, and 4-wide AND-OR Structure

42. Example(PAL)

43. Fuse Map for PAL

44. 7-8 SEQUENTIAL PROGRAMMABLE DEVICES
SPLD(Sequential (or Simple) Programmable Logic Device)
It Includes FFs within IC chips + AND-OR array
CPLD(Complex Programmable Logic Device)
It consists of multiple PLDs interconnections through a programmable switch matrix.
FPGA (Field Programmable Gate Array)
A VLSI circuit that can be programmed in the user’s location

45. SPLD

46. Basic Macro cell
PAL

47. CPLD
CPLD-a collection of individual PLDs

48. FPGA(Field Programmable Gate Array)
It consists of
Look-up tables
Multiplexes
Gates
Flip-flops