Issues in FPGA Technologies

Slides:

Advertisements

Similar presentations

ECE 506 Reconfigurable Computing ece. arizona

Advertisements

Lecture 15 Finite State Machine Implementation

Reconfigurable Computing (EN2911X, Fall07) Lecture 04: Programmable Logic Technology (2/3) Prof. Sherief Reda Division of Engineering, Brown University.

Xilinx CPLDs and FPGAs Module F2-1. CPLDs and FPGAs XC9500 CPLD XC4000 FPGA Spartan FPGA Spartan II FPGA Virtex FPGA.

Survey of Reconfigurable Logic Technologies

Spartan II Features  Plentiful logic and memory resources –15K to 200K system gates (up to 5,292 logic cells) –Up to 57 Kb block RAM storage  Flexible.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR SRAM-based FPGA n SRAM-based LE –Registers in logic elements –LUT-based logic element.

Implementing Logic Gates and Circuits Discussion D5.1.

Implementing Logic Gates and Circuits Discussion D5.3 Section 11-2.

Lecture 2: Field Programmable Gate Arrays I September 5, 2013 ECE 636 Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays I.

Silicon Programming--Altera Tools1 “Silicon Programming“ programmable logic Altera devices and the Altera tools major tasks in the silicon programming.

Programmable logic and FPGA

Silicon Programming--Altera Tools1 “Silicon Programming“ programmable logic Altera devices and the Altera tools major tasks in the silicon programming.

Implementing Digital Circuits Lecture L3.1. Implementing Digital Circuits Transistors and Integrated Circuits Transistor-Transistor Logic (TTL) Programmable.

Xilinx CPLDs and FPGAs Lecture L1.1. CPLDs and FPGAs XC9500 CPLD Spartan II FPGA Virtex FPGA.

ALTERA UP2 Tutorial 1: The 15 Minute Design. Figure 1.1 The Altera UP 1 CPLD development board. ALTERA UP2 Tutorial 1: The 15 Minute Design.

05/12/06BR Fall 991 Programmable Logic So far, have only talked about PALs (see 22V10 figure next page). What is the next step in the evolution of PLDs?

Lecture 2: Field Programmable Gate Arrays September 13, 2004 ECE 697F Reconfigurable Computing Lecture 2 Field Programmable Gate Arrays.

DSD Presentation Introduction of Actel FPGA. page 22015/9/11 Presentation Outline  Overview  Actel FPGA Characteristic  Actel FPGA Architecture  Actel.

EE4OI4 Engineering Design Programmable Logic Technology.

Section II Basic PLD Architecture. Section II Agenda  Basic PLD Architecture —XC9500 and XC4000 Hardware Architectures —Foundation and Alliance Series.

Programmable chips and boards

Electronics in High Energy Physics Introduction to Electronics in HEP Field Programmable Gate Arrays Part 1 based on the lecture of S.Haas.

System Arch 2008 (Fire Tom Wada) /10/9 Field Programmable Gate Array.

J. Christiansen, CERN - EP/MIC

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR FPGA Fabric n Elements of an FPGA fabric –Logic element –Placement –Wiring –I/O.

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

Sept. 2005EE37E Adv. Digital Electronics Lesson 1 CPLDs and FPGAs: Technology and Design Features.

BR 1/991 Issues in FPGA Technologies Complexity of Logic Element –How many inputs/outputs for the logic element? –Does the basic logic element contain.

BR 1/991 Logic Element array PIN Altera IO Element.

CPLD Vs. FPGA Positioning Presentation

M.Mohajjel. Why? TTM (Time-to-market) Prototyping Reconfigurable and Custom Computing 2Digital System Design.

ESS | FPGA for Dummies | | Maurizio Donna FPGA for Dummies Basic FPGA architecture.

Introduction to Field Programmable Gate Arrays Lecture 1/3 CERN Accelerator School on Digital Signal Processing Sigtuna, Sweden, 31 May – 9 June 2007 Javier.

FPGA: Field Programmable Gate Array

EE121 John Wakerly Lecture #15

Delivered by.. Love Jain p08ec907. Design Styles  Full-custom  Cell-based  Gate array  Programmable logic Field programmable gate array (FPGA)

FPGA-Based System Design: Chapter 3 Copyright  2004 Prentice Hall PTR Topics n FPGA fabric architecture concepts.

Field Programmable Gate Arrays

Sequential Programmable Devices

Reconfigurable Architectures

Lecture 15 Sequential Circuit Design

Topics SRAM-based FPGA fabrics: Xilinx. Altera..

Complex Programmable Logic Device (CPLD) Architecture and Its Applications

Design for Embedded Image Processing on FPGAs

Give qualifications of instructors: DAP

XILINX FPGAs Xilinx lunched first commercial FPGA XC2000 in 1985

ECE 4110– 5110 Digital System Design

Electronics for Physicists

ELEN 468 Advanced Logic Design

Field Programmable Gate Array

Field Programmable Gate Array

Field Programmable Gate Array

Figure 3.1 Digital logic technologies.

Figure 3.1 Digital logic technologies.

We will be studying the architecture of XC3000.

Chapter 13 – Programmable Logic Device Architectures

CPE 528: Session #12 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

The Xilinx Virtex Series FPGA

Figure 3.1 Digital logic technologies.

XC4000E Series Xilinx XC4000 Series Architecture 8/98

FIGURE 7.1 Conventional and array logic diagrams for OR gate

The architecture of PAL16R8

CPE 528: Session #10 Department of Electrical and Computer Engineering University of Alabama in Huntsville.

The Xilinx Virtex Series FPGA

Electronics for Physicists

Exploring Application Specific Programmable Logic Devices

Implementing Logic Gates and Circuits

FPGA’s 9/22/08.

Programmable logic and FPGA

Presentation transcript:

Issues in FPGA Technologies Complexity of Logic Element How many inputs/outputs for the logic element? Does the basic logic element contain a FF? What type? Interconnect How fast is it? Does it offer ‘high speed’ paths that cross the chip? How many of these? Can I have on-chip tri-state busses? How routable is the design? If 95% of the logic elements are used, can I route the design? More routing means more routability, but less room for logic elements BR 1/99

Issues in FPGA Technologies (cont) Macro elements Are there SRAM blocks? Is the SRAM dual ported? Is there fast adder support (i.e. fast carry chains?) Is there fast logic support (i.e. cascade chains) What other types of macro blocks are available (fast decoders? register files? ) Clock support How many global clocks can I have? Are there any on-chip Phase Logic Loops (PLLs) or Delay Locked Loops (DLLs) for clock synchronization, clock multiplication? BR 1/99

Issues in FPGA Technologies (cont) What type of IO support do I have? TTL, CMOS are a given Support for mixed 5V, 3.3v IOs? 3.3 v internal, but 5V tolerant inputs? Support for new low voltage signaling standards? GTL+, GTL (Gunning Tranceiver Logic) - used on Pentium II HSTL - High Speed Transceiver Logic SSTL - Stub Series-Terminate Logic USB - IO used for Universal Serial Bus (differential signaling) AGP - IO used for Advanced Graphics Port Maximum number of IO? Package types? Ball Grid Array (BGA) for high density IO BR 1/99

Altera FPGA Family Summaries Altera Flex10K/10KE LEs (Logic elements) have 4-input LUTS (look-up tables) +1 FF Fast Carry Chain between LE’s, Cascade chain for logic operations Large blocks of SRAM available as well Altera Max7000/Max7000A EEPROM based, very fast (Tpd = 7.5 ns) Basically a PLD architecture with programmable interconnect. Max 7000A family is 3.3 v BR 1/99

Xilinx FPGA Family Summaries Virtex Family SRAM Based Largest device has 1M gates Configurable Logic Blocks (CLBs) have two 4-input LUTS, 2 DFFs Four onboard Delay Locked Loops (DLLs) for clock synchronization Dedicated RAM blocks (LUTs can also function as RAM). Fast Carry Logic XC4000 Family Previous version of Virtex No DLLs, No dedicated RAM blocks BR 1/99

Actel FPGA Family Summaries MXDS Family Fine grain Logic Elements that contain Mux logic + DFF Embedded Dual Port SRAM One Time Programmable (OTP) - means that no configuration loading on powerup, no external serial ROM AntiFuse technology for programming (AntiFuse means that you program the fuse to make the connection). Fast (Tpd = 7.5 ns) Low density compared to Altera, Xilinx - maximum number of gates is 36,000 BR 1/99

Cypress CPLDs Ultra37000 Family 32 to 512 Macrocells Fast (Tpd 5 to 10ns depending on number of macrocells) Very good routing resources for a CPLD BR 1/99