SOCLE Meeting Dec Roman Pöschl LAL Orsay On behalf of the groups performing Electronics R&D - Introduction - SKIROC2 – Handling the large Dynamic Range - PCB Development – Ultra thin Solutions - ADC Developments – Fast and efficient readouts - Summary and Conclusion Electronics Development for SiW Ecal SOCLE Meeting LAPP Annecy Dec Material for this talk provided by: D. Dzahini, J. Fleury, L. Royer, C de la Taille

18 june 08C. de La Taille SPIROC : SiPM readout ASIC NDIP08 Aix les Bains 2 ILC Challenges for electronics Requirements for electronics –Large dynamic range (15 bits) –Auto-trigger on ½ MIP –On chip zero suppress –Front-end embedded in detector –Ultra-low power : («25µW/ch ) –10 8 channels –Compactness « Tracker electronics with calorimetric performance » No chip = no detector !! ATLAS LAr FEB 128ch 400*500mm 1 W/ch FLC_PHY3 18ch 10*10mm 5mW/chILC : 25µW/ch W layer ASIC Si wafers Ultra-low POWER is the KEY issue

SOCLE Meeting Dec Main “tool” - Power Pulsing: - Electronics switched on during 1ms of ILC bunch train and subsequent signal propagation - Electronics IDLE in time between bunch trains

18 june 08C. de La Taille SPIROC : SiPM readout ASIC NDIP08 Aix les Bains 4 The front-end ASICs : the ROC chips SPIROC Analog HCAL (SiPM) 36 ch. 32mm² June 07 HARDROC Digital HCAL (RPC, µmegas or GEMs) 64 ch. 16mm² Sept 06 SKIROC ECAL (Si PIN diode) 36 ch. 20mm² Nov 06 Technological prototypes : full scale modules (~2m) EUDET EU funding (06-09) ECAL, AHCAL, DHCAL

SOCLE Meeting Dec SKIROC1 One channel block scheme 1MΩ 0  6pF Preamp. Input 20MΩ 3pF Calib.Input 10-bit dual DAC – common to 36 channels Analog Memory Depth = 5 Analog Memory Depth = 5 12-bit ADC (Wilkinson) Trigger out Charge Meas. Gain selection Slow shaper Gain 10 T p =180ns Slow shaper Gain 1 T p =180ns Amplifier Gain 5 fast shaper Gain 100 T p =100ns 3-bit DAC adjustment Issue: Initial design of Preamp could not sustain the large dynamical range required

SOCLE Meeting Dec Parallel Developments SKIROC replaced by SPIROC Advantage: - Maintain the speed of EUDET Module construction - Allow to study issues beyond Chip development Progress on PCB development Interplay SiW PCB Chip Drawbacks: - Small Dynamic Range 500 MIPs - Smaller Channel Number - Higher Noise SKIROC1 SKIROC Channels 4 Chips/Wafer SKIROC is the biggest ROC!!! - Will be operated in “ILC Mode” and Testbeam Mode - Might need dedicated structures of testbeams - Dynamic Range MIPS - Possibility to add Timestamps Benefit from SPIROC

SOCLE Meeting Dec SKIROC 2 block scheme proposal 1MΩ 2 pF Preamp. Input 20MΩ 3pF Calib.Input 10-bit dual DAC – common to 64 channels Analog Memory Depth = bit ADC (Wilkinson) Trigger out Charge Meas. Gain selection Slow shaper Gain 1 T p =180ns fast shaper Gain 100 T p =100ns 3-bit DAC adjustment 8 pF We already have that kind of structure on the shelf Time Measurement ? Everything in hand (from spiroc) Peak sensing High gain : 0.5  500 MIP Low gain : 500  2500 MIP

SOCLE Meeting Dec Injection : 1000MIP, Low gain, High Gain (saturated), auto Gain Preamp & slow shaper (preliminary simulation) Active Gain Adjustment in SKIROC2

SOCLE Meeting Dec Schedule ● Skiroc 2 expected to be sent in fab in March’09 – Sharing of the HARDROC2 and SPIROC2 production – If SKIROC 2 is validated  production in hand for EUDET module – Cheaper than an engineering run for prototyping due to big silicon area (60mm² ie ~60k€) ● Next PCB prototype will use SPIROC2 with Hamamatsu wafers – Validation of all electronics and assembling process – missing : dynamic range (500MIP/2500MIP), granularity – PCB in hand before the end of the year ?

SOCLE Meeting Dec PCB Design – First Prototype FEV5 Main Purposes: - Learn how to fabricate highly compact PCBS - Test interplay with DAQ components 180.5mm Issues: - Demand for compactness goes beyond industrial standards - Unable to bond Chip onto PCB, lack of gold in one of the layers Remedy? Encouraging “contact” with Corean Groups

SOCLE Meeting Dec Chip Embedding + PCB Pile-up 3 drilling sequences : - Laser C7-C8 120µ filled - Laser C6-C7 120µ - Mechanical C1-C7 Pile-up TOPGND+routing C2AVDD+routing C3AVDD+DVDD C4GND + horizontal routing C5AVDD+ vertical routing C6GND+pads routing C7GND (pads shielding) BOTPADS

SOCLE Meeting Dec Issues : Layer 2 not bondable Cross Cross Section through one Pin Copper Nickel Intensive Investigation between LAL, CERN and Manufacturer

SOCLE Meeting Dec FEV7 wafer footprint FEV7 EUDET Compliant PCB 144 Channels 4x36 Will be used for Si Wafer characterization Several pads ganged together Need SPIROC2 validation

SOCLE Meeting Dec Concluding Remarks on PCB Development ● PCB design – FEV5 engineering done – NOT SO EASY TO BUILD  still not validated – Opportunity to have 256 ch. Wafers ? (5.5mm pads) ● For FEV8 design ● To be available in Spring 09 – FEV7 design using Hamamatsu Wafer and Spiroc 2 in 2008

SOCLE Meeting Dec  Main requirements for the ADC: –Ultra low power:  2.5µW/ch (10% of the VFE power budget)  Power pulsing needed –Resolution:  10 bits if 3-gain shaping  12 bits if 2-gain shaping –Time of conversion: time budget of 500 µs to convert all data of all triggered channels –Die area:  as small as possible… (0.225 mm2 per each channel of Skiroc without ADC) Beyond EUDET Towards ILC – ADC(s) for VFE Analog electronics busy 1ms (.5%) A/D conv..5ms (.25%) DAQ.5ms (.25%) IDLE MODE 198ms (99%)

SOCLE Meeting Dec Proposal: one ADC per channel Short analog sensitive wires from memory to ADC A digital Data Bus far from sensitive analog signals Only ADCs of triggered channels powered ON Conversions of channels done in parallel Integrity of analog signals saved Power saved  Pedestal dispersion of ADC "added" to the dispersion of the analog part …. but calibrated With one-ADC-per-channel architecture: No "fast" ADC required

SOCLE Meeting Dec Two candidates for the architecture of the ADC Pipeline ADC Cyclic ADC

SOCLE Meeting Dec A 12-bit cyclic ADC (1) 18 The 12-bit cyclic ADC prototype designed and LPC Clermont:  Technology: 0.35 µm CMOS Austriamicrosystems  A cyclic architecture: well-adapted to the implementation of one ADC per channel  1.5 bit architecture  relaxed constraints on offsets of comparators  Power pulsing system implemented Layout of the chip Main characteristics:  Technology: 0.35 µm CMOS Austriamicrosystems  Resolution: 12 bits  Power consumption: 4 mW / 3.5V  Time of conversion: 6 µs  Area: 0.175mm 2

SOCLE Meeting Dec A 12-bit cyclic ADC (2)  Performance of the cyclic ADC:  Improved architecture: calculation of two bits during one clock period  Time of conversion: 7µs w/ 1MHz clock freq.  1 ampli. + 2*2 comp. + 2 capacitors arrays  Consumption: 4 mW/3.5V  Integrated cons. with power pulsing: 0.7 µW with analog memory depth of 5 events 2.2 µW with analog memory depth of 16 events  Area: mm conversion phases with a single ampli. 1 clock period (1) 12 7 clock periodsTime for one conversion Area Integrated power Power consumption Resolution 12 down to  10 (3) 1  down to  6 (2) 12  down to  6 (2) 1  bits PipelineOptimized Cyclic

SOCLE Meeting Dec MHz clock "Start conversion " signal Oscillogram of the chip under test Very First results of measurement

SOCLE Meeting Dec Cyclic ADC – Non Linearity and Noise INL – Integral Non Linearity Measurement Simulation Code 1V Standard deviation = 0.84 LSB (420µV) DNL – Differential Non Linearity < 2Bit < 1Bit

SOCLE Meeting Dec  Only an extra-time of 1 µs required to perform one conversion  Time of conversion: 6µs  7µs Power pulsing system on master current sources Measurement of consumption vs duty cycle Consumption with power pulsing

SOCLE Meeting Dec Versions of 25MHz, 12 bit, 2V pp Pipeline ADC Version 1: Full 1.5 bit per stage Version 2: With a multi bit 2.5 bits /stage

SOCLE Meeting Dec Measurement Test of Pipeline ADC DNL: < 1 LSB INL: < 4 LSB 2V - Power supply could be reduced => Extra Power Saved - Wide noise margin

SOCLE Meeting Dec Average Power Pulsing Budget T TC (Total Time conversion) = 40ns x 64 x 16 = 41µs ADC Power Consumption per chip = ((P ADC +P MUX ) x T TC )/200ms/64ch 141nW/channel Memory depth= 16 # of channel = 64 T c =40ns P ADC =37mW With Power pulsing P MUX =7mW 64

SOCLE Meeting Dec bits Sigma Delta DAC 16 bits with INL= +/- 4LSB Fine results but an integrated filter is needed to generate a DC signal This is not trivial, this is why we consider another architecture “C 2 C”

SOCLE Meeting Dec bits 4MHz Segmented capacitors DAC for Calibration This 12 bits is the basis to go forward To a 14 and 16 bits version. 12 bits with INL= +/- 0.4LSB

SOCLE Meeting Dec Summary and Conclusion - Rich R&D Program on Electronics for SiW Ecal in France - Performed within the CALICE Collaboration - Large synergies with needs for other Calorimeter Types “ROC Family” - R&D for EUDET exhibited already significant technological obstacles - Large dynamic range - Ultra thin layers Problems about to be overcome - EUDET Prototype constitute crucial test device for the validation of the main concepts - Interleaved VFE Electronics - Power Pulsing - R&D on efficient ADCs/DAC point already to the time beyond EUDET Module - “Third” generation of Prototypes - Integration into current activities