UNI EN ISO 9001 CERT. N CAEN New Developments in Waveform Digitizers Matteo M. Angarano

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Outline Analogue vs Digital Why Waveform Digitizers? Boards overview Conclusions

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Typical DAQ Detect. Amp FI/FO Discr. Detector Amp/Att Discr. FI/FO TRA Logic DelayADC Timing C. Start Enable Scaler TDC ST Conv Trigger section I/O Reg

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Analog vs. Digital Detect. + Analog Shaping Amplifier + ADC MCA Detect. + flash ADC Digital Pulse Shape Analysis Digital Filter Pulse Analysis MCA FPGA

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Digital DAQ Higher rate pile-up rejection dead time baseline restoration Higher dynamic range More information and greater flexibility complex algorithms implementation of complex trigger schemes Higher stability and reproducibility Higher channel density and increased reliability

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Digital Techniques Spectroscopy –Pulse Shape Analysis –Optimisation of pulse shaping parameters –Ballistic deficit correction –Correction of charge trapping effects –Time stamp and counting rate information (fADC as a TDC) Particle identification –Rise time / energy correlation –Rise time discrimination –Double charge method –Likelihood ratio methods –Neural network methods Tracking –Gamma ray tracking in segmented germanium detectors –Depht Of Interactions measurements –Locate Compton scattering

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited List (partial!) of experiments using or planning to use waveform digitizers: –Nuclear spectroscopy (AGATA, GRETA, CHIMERA, FAZIA, FRIBs, RISING, SAGE, …) –Reactor (DoUble Chooz, …) –Underwater (ANTARES, NEMO, Km 3, GVD, …) –0  decay (Majorana, …) –Dark matter (XENON, WARP, ArDM, …) –Cherenkov telescopes (MAGIC, HESS, CTA, …) –HEP (MeG, NA62, …) –R&D for neutrino factory (MICE, …) –R&D for International Linear Collider detectors –Nuclear fusion Tokamak (MAST, …) –Positron Emission Tomography Applications

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited CAEN Waveform Digitizers (1) WD = Waveform Digitizer PSA = Pulse Shape Analysis (2) Total memory for 4 channels (3) To be confirmed

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited MOTHER BOARD Structure One common mother board housing 4 specific mezzanine cards VME / O.L. POWER SUPPLY CLOCK MANAGER LOCAL BUS MEZZANINES ADC ACQ. CTRL MEM ADC ACQ. CTRL MEM ADC ACQ. CTRL MEM ADC ACQ. CTRL MEM FPGA READOUT LOGIC TRIGGER LOGIC PANEL I/Os VME / OL INTERFACE

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Layout PLL FPGA Opt. Link LOCAL BUS DC-DC ADC FPGA Memory Lin. Reg. DC-DC I/Os CLK in CLK out VME

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Analog Input Specs Single ended (MCX - 50  ) or differential (Modu II  ) 1 st or 2 nd order low pass Fs/2 Programmable DAC for DC level adjust Positive, negative and bipolar signals Fixed gain Different input dynamic ranges on request

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Clock features All differential signals  Very Low Jitter! Internal and External clock source Programmable PLL for clock synthesis Direct drive option (PLL bypass) Programmable phase shift for multi-board clock alignment Daisy chain clock distribution: one board acts as clock Master

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Trigger features External NIM/TTL Trigger Input / Output Digital auto trigger from each channel Trigger propagation from one channel/board to the others Analog linear sum or majority output for global trigger logic Digital I/Os for trigger tagging or digital majority Programmable Pre and Post-trigger windows Accept/Reject overlapping triggers 1 to 1024 memory buffers (events) 32 bit Trigger Time Stamp

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Global Trigger Global Trigger Logic AnalogΣ Trigger UNIT Mod. V1495 MON/Σ TRG_OUT MON/Σ V17XXDigitizer TRG_OUT Digital I/O V17XXDigitizer TRG_IN

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Acquisition window Programmable Record length and Pre trigger size Deadtime-less event recording Zero suppression algorithms

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Zero Suppression Programmable Thresholds and Windowing Full suppression: one event can be fully suppressed if the signal (or its integral) does not exceed the threshold Zero Length Encoding: only the parts exceeding the threshold (plus some samples before and after) are saved.

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Optical Link Full replacement of the VME interface 80 MB/s throughput rate (exp. up to 125 MB/s) Daisy Chainable Network (CONET ) PCI Optical Link controller available from the catalog (A2818 ) One A2818 can control up to 8 ADC modules (64 channels) Firmware Upgrade via O.L. for all FPGAs

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited 12 bit, 100MS/s DAC LEMO coaxial output (driving 50  5 operating modes: Analog sum of the inputs (with enable mask) Majority (number of channels over threshold) Memory occupancy monitor Test pattern generator (full scale triangular wave) Programmable constant voltage level Analog Inspection

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Runtime baseline calculation and subtraction Jordanov's trapezoidal filters for the energy extraction Pole-zero cancellation Digital CFD for timing information Online histogram building Advanced trigger: pulse height, energy... The ADC channel structure allow the implementation of FPGA based digital filtering and signal process. In principle it is possible to implement: Pulse Shape Analysis Close interaction  heavy support from CAEN needed! Allow the user to program the FPGA? Full control Need to know the hardware Embedded code Need to share the VHDL code

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited CAENScope: a multi-platform demo Open source Library with basic functions for settings and readout Acquisition sample programs Windows and Linux supported Labview VI's Utilities (PLL configuration, firmware upgrade...) Software

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited 16 channel LVDS programmable In/Out 100  built-in termination 34 conductor, 0.05” pitch flat cable 4x4 I/O register External Trigger TAG Outputs for external trigger logic (global triggering) Control signals: Busy, Veto, Local Triggers, Timer Reset... Digital I/Os

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited VME interface VME64X compliant A24, A32, CR/CSR addressing modes Single cycle D32, BLT, MBLT (up to ~60MB/s) 2eVME, 2eSST (up to ~160MB/s) Broadcast Write Chained Block Transfer VME64 and VME64X mechanics Firmware Upgrade via VME for all FPGAs Multi-board access

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Clock distribution diagram

Reproduction, transfer, distribution of part or all of the contents in this document in any form without prior written permission of CAEN S.p.A. is prohibited Trigger block diagram