1. VLVNT08 Toulone April 2008
Low Power Multi-Dynamics Front-End Architecture for the OM of a Neutrino Underwater Telescope
Domenico Lo Presti
Istituto Nazionale di Fisica Nucleare - Catania
University of Catania – Physics Depart. - Microelectronics Group
University of Bologna – Physics Depart. -Electronics Group

2. Overview Main Goals Proposed Architectures Test & validation
VLVNT08 Toulone April 2008
Overview
Main Goals
Proposed Architectures
Test & validation
NEMO phase 2
Conclusions

3. FE - Main Goals FE electronics inside the Optical Module.
VLVNT08 Toulone April 2008
FE electronics inside the Optical Module.
Low Power Dissipation (<500 mW per OM)
Signal waveform up to 720 ns – SAS (Smart Autotriggering Sampler) chip Msps
Multiple Dynamics
3 linear dynamic ranges up to 512 pe
charge dynamic range up to pe
Signal classification
Negligible Dead Time (up to 300 KHz BG in 10” PMT)
5 ns Time stamp online
300ps Time stamp offline
Low PMT Gain required
Higher linear dynamic range
lower Dark current and higher operating life

4. VLVNT08 Toulone April 2008
FE - SAS block diagram

5. FE-SAS Sampling Strategy
VLVNT08 Toulone April 2008
FE-SAS Sampling Strategy
3 sampling modes:
SAS_SHORT
4 independent memory banks: START (T&SPC)
3 channels 16 cells
200 MHz sampling 20 MHz transfer
Serial transfer towards ADC
SAS_LONG
T&SPC enabled: signal over Threshold more than 60 ns
3 channels 128 cells
FADC (external 12b 20 MHz ADC)
T&SPC enabled: signal over Threshold more than 720ns
Integrated signal
10 bit 20 MHz Flash ADC
16 Ksamples record length

6. SAS (Smart Autotriggering Sampler)
VLVNT08 Toulone April 2008
SAS (Smart Autotriggering Sampler)

7. Analogue Memory 1 11 memory modules – 3 channel 16 cells each.
VLVNT08 Toulone April 2008
11 memory modules – 3 channel 16 cells each.
Input Buffer
Memory bank
Output Buffer
The module (bank) contains (500mm x 500mm):
3x16 memory cells (each cell 500fF + 4 switches)
1 write address shifter (dynamic)
1 read address shifter (static)
Encoding logic
1 bank OTA
The banks are arranged in a 3x4 matrix (2x3 mm2)

8. Analogue Memory 2 200 MHz sampling freq. 20 MHz transfer freq.
VLVNT08 Toulone April 2008
200 MHz sampling freq. 20 MHz transfer freq.
Asynchronous and event-driven Control Unit on chip.
Active only on SOT leading edge
200 MHz is not distributed until it is active
Write mode is controlled by SOT and the classification bits
Read mode is controlled by the FPGA Control Unit
Total area < 10 mm2
Total power consumption < 60 mW 3,3 V)
Input dynamic range is rail to rail, linear up to MHz

9. Proposed Architecture - PMT Interface
VLVNT08 Toulone April 2008
Proposed Architecture - PMT Interface
-3dB
-60dB
Protection -2 x1 /8
/64 R1 R2 R3
Filter
Delay
OUT A
OUT B
OUT C Ra Rb -1
Integrator
Rtot =
300W
-3dB
-60dB
IC Delay Line 30 ns 3

10. PMT interface - measurements
VLVNT08 Toulone April 2008
PMT interface - measurements
< 8 pe
8 pe ÷ 64 pe
Integrator
PMT R7081sel
ISEG HV base
Gain 1•107
64 pe ÷ 512 pe
> 512 pe

11. Trigger & Single Photon Classifier
VLVNT08 Toulone April 2008
Trigger & Single Photon Classifier
B0, B1, B2 = PMT signal classification code
SOT, Signal Over Threshold, twofold use:
Rising edge Trigger;
SOT width determines sampling mode (Short, Long, Integ.)
Th0 e Th1 generated by 2 6-bit DAC serial code (Slow Control).
Th0 trigger threshold;
Th1 Out of range threshold.
Asynchronous and always active.
Out A
Out B
Out C
Th1
Th0 B2 B1 B0
SOT
Fast comparator with hysteresis

12. FE-ADC vs FE-SAS Different solutions for sampling SAS SCA vs flash ADC
VLVNT08 Toulone April 2008
Different solutions for sampling
SAS SCA vs flash ADC
Power consumption
Same solutions for the other items in the board.
SAS simulated power consumption
-> 60 3,3 V!
AD9230 power consumption
480 1,8 V

13. VLVNT08 Toulone April 2008
FE-ADC block diagram

14. FE-ADC Sampling strategy
VLVNT08 Toulone April 2008
FE-ADC Sampling strategy
ADC always 200 MSPS
Signal to be sampled selected by the analog multiplexer on the basis of classification
Sampling when signal over threshold.
Autoranging – signal dynamic range changes during sampling
5ns Time stamp and classification encoded for any event.
Data stored in FPGA RAM 16 Kb.
When RAM full – event rate available

15. FE - ADC Dual safe boot & power supply ctrl. PMT ctrl. & mon. Sensors
VLVNT08 Toulone April 2008
FE - ADC
PMT INTERFACE
ANALOG MULTIPLEXER
TSPC
ADC-AD9230
FPGA-XC3S400
EXT. CONNECTIONS
Sensors
PMT ctrl. & mon.
Dual safe boot
& power supply ctrl.

16. Main features and test results
VLVNT08 Toulone April 2008
Interface to Floor Control Module – under test
Power supply (analog and digital) - √ V
187 mA ADC
Dual Safe Boot - √ FPGA back-up firmware
PMT ctrl. (ISEG base interface) - √
PMT interface - √
T&SPC - √
ADC 200 Msps 12 bit - √
200 MHz lvds Sampling clock generation (DCM) - √
Time Stamp & classification (SC settable) - √
Temp. & Hum. Sensors - √
Istantaneous Rate monitor - √
Test bench – under development

17. NEMO phase 2 – site and apparatus
VLVNT08 Toulone April 2008
NEMO phase 2 – site and apparatus

18. DATA TRANSMISSION Sea Shore
VLVNT08 Toulone April 2008
DATA TRANSMISSION
FEM#0
FEM#1
Sea
Data from the Optical Modules come from 4 (up to 8) Front End Modules (FEM) 1
Floo data concentration off-shore is performed by the Floor Control Module (FCM)
Data coming from one floor are received on-shore by a twin FCM board, plugged in a pc (FCM Interface) 2
At FCMI, data are stored in a memory buffer (Front End Buffers, or FEB). Each FEB contains formatted data coming from the correspondent FEM.
FEM#2
FEM#3
Shore
Data Manager 3
FEB#0
FEB#1
FEB#2
FEB#3
Master CPU
FCMI

19. VLVNT08 Toulone April 2008
Conclusions
The FE-SAS electronics architecture has been defined and almost full designed;
ASIC ready soon (march 2008 AMS RUN);
The FE-ADC board is ready and under test;
All the goals apart from low power consumption can be fulfilled.
Test & Validation in Optical module.
4 FE-ADC in one floor of NEMO phase 2 tower.

20. VLVNT08 Toulone April 2008
Thank You

21. Preliminary measurement
VLVNT08 Toulone April 2008
Preliminary measurement

22. Charge spectra Rate 137 KHz Channel A σ : 0.38 pC resolution: 2.1%
VLVNT08 Toulone April 2008
Charge spectra
Rate 137 KHz
Channel A
σ : 0.38 pC
resolution: 2.1%
Rate 224 KHz
channel A
σ : 0.41 pC
resolution: 1.6%

23. Leading edge and baseline reconstruction
VLVNT08 Toulone April 2008
Gaussian fit:
Leading edge and baseline reconstruction

24. FE linear dynamic range
VLVNT08 Toulone April 2008
FE linear dynamic range

25. Fine Timestamp resolution
VLVNT08 Toulone April 2008
Fine Timestamp resolution
st (* 5 ns) = ps

26. Dark current in a dark box: R7081 SEL
Next measurements
VLVNT08 Toulone April 2008
Dark current in a dark box: R7081 SEL
PMT 7081 SEL with ISEG base
“Mini Dark Box” and FEM Board.

27. VLVNT08 Toulone April 2008
CHB

28. VLVNT08 Toulone April 2008
Reconstruction
CHA
CHB