October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology KM3NeT CLBv2 1

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology ICAPE2 2 Very first Read cycle to ICAPE2 failed. Empirically found that the module needs an Abort sequence after Rst. Information from Xilinx-FEA was not really helpful. Documentation keeps being crappie. Newest multiboot sources should work (SVN rev. 1201)

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology TestGui Firmware image update 3 CLBV2_2_1: ◦ 2.26, 2.28, 2.32, 2.33, 2.34, 2.35, 2.36, 2.37, 2.38, 2.39 and 2.40 fail to configure after configuration via the TestGui. Procedure:  Upload tagged rev140917_00 via Xilinx Download Cable: make TARGET=CLBV2_2_1 upload  Fimware update image 0 and 1 via TestGUI  Re-power => fail to configure! Investigation… Use Impact once to program an “MCS” file to the Flash memory. Next using the TestGui works fine !? Was the Flash locked or put into an unknown state during production and testing? What tests were done and what firmware was on each of them? Definitely something to sort out further! We need an Elog per “electronics-item”!

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology StMach Front-end Enables 4 Front-End enable gets asserted, the clock tick after “time-slice start” such that the first enabled “Time-Slice" marker is not written into the front-end FIFOs although it is written to the Time-Slice FIFO (storing the Time Slice time stamp). Enables are handles per Time-Slice Verified that TDC/AES/MCH start/stop properly. Verified with David. State Machine might need a cleanup of the source code. Time-Slice Start LM32 Enable Time-Slice FIFOs (We) Front_end Enables Front-End Time-Slice markers

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Possible Auto Negotiation deadlock 5 In the future it should be possible to communicate between the WR- LM32 and the LM32-2 nd (Slow-Control) to set for example yes/no Auto Negotiation. The possible dealock: If I remember well: ◦ The broadcast switch setup needs AutoNeg “off”. ◦ Standard switch setup (at least a WR switch) needs AutoNeg “on”. Also something to sort out further… We need a link that is UP to change the AutoNeg setting via Slow-Control The link only gets UP if AutoNeg has the proper setting

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Todo list 6 Fix State Machine, TDC, AES and MCH (David, Antonio, me) Re-arrange MCH channel (proper time-tag; not lagging one time-slice => me) Flow-Control study: ◦ define system level actions when frontends overflow ◦ Implementing LM32 IRQ (Front-End FIFO full status) ICAPE2 / multiboot / watchdog / golden image tests Software: Communication interface between LM32_2 nd and LM32_WR ◦ SFP readout and setting (loopback, PRBS, wavelength tuning) ◦ Auto negotiation control (pay attention to deadlock) Ethernet flow control (received pause frame implementation in the CLB)

October 29, 2014CLBv2, Vidyo Peter Jansweijer Nikhef Amsterdam Electronics- Technology Backup slides 7