1. Normal text - click to edit Status Report TPC Electronics Meeting, CERN 21.04.06 Johan Alme & Ketil Røed, UoB

2. Normal text - click to edit Outline DCS firmware RCU Aux FPGA firmware Status

3. Normal text - click to edit Readout Control Unit

4. Normal text - click to edit DCS Firmware Firmware is now in version 2.4 Minor updates since last revision –Timing on RCU Flash Interface made less tight –Triple redundancy on some critical registers –RCU Interrupt handling in final version –FW version register (readable in mem mapped mode) –Eventcount Reset/Bunchcount Reset from TTCrx available for RCU. Also generated from Serial B messages on trigger receiver module on RCU. –Generic Memory Size on compile time –Increased timeout period of RCU mem mapped communication to 32 clks

5. Normal text - click to edit RCU Aux FPGA FW Firmware version 1.2 is ready. ALL features included –Initial Configuration –Scrubbing of complete configuration supported: single Continuous until abort Continuous # number of cycles –Readback frame by frame verification and correcting supported: Single step. One frame at the time Continuous until abort. Runs complete cycles (all frames). Continuous # number of times. Runs complete cycles.

6. Normal text - click to edit RCU Aux FPGA FW

7. Normal text - click to edit Test of Scrubbing Made a test design for the Xilinx that included: –Registers (possible to scrub) –BRAM (scrubbing will not touch these) –LUT-RAM (not possible to scrub and should not be used) With ISE-tool generated file for: –Initial configuration –scrubbing (complete active partial reconfiguration) Verified that registers and bram held their value during scrubbing, while LUT ram did not. As expected. Also did a short test of scrubbing with real RCU design, where we did not see the scrubbing affect the operation of the firmware at all – which is good.

8. Normal text - click to edit Test of Readback Verification Generated 10 single frames files and stored on the Flash. –5 x Including read header & footer. ”Read frame” –5 x Including write header & footer. ”Write frame” Verification test: –Implanted errors in the read frames on the Flash. –Counted number of differences between files on Flash and readback result from Selectmap Reconfiguring test: –Implanted errors in both write and read frame. Differences were found between Xilinx and Flash. Reconfiguring started automatically. –Readback Xilinx after reconfiguring  Errors implanted in Xilinx

9. Normal text - click to edit Some Preliminary Numbers Init Configuration (filesize: 560kb) : ~43 ms Scrubbing (filesize: 221kb):~16 ms –Note: Dependent on filesize Read and verify 1 frame: ~90 us Read, verify and correct 1 frame: ~160 us Total number of frames to verify/correct: –IOB: 8, IOI: 44, CLB: 748, BRAM IC: 132, GCLK: 4 –SUM: 936 Read and verify all frames: ~84 ms Read, verify and correct all frames: ~150 ms –Extremely unlikely. Number of errors per Xilinx per 4 hrs run: ~0.03 Max number of Readback/verification cycles per 4 hrs run: –171500 (no errors) –96000 (always errors in all frames)

10. Normal text - click to edit Status RCU Aux FPGA: –All functionality in place. –Functionally verified and under test since last week. –Documentation in progress –Final version available. DCS FW: –All functionality in place. –Documentation in progress

11. Normal text - click to edit Additional features in v1.2 Counters for Number of Readback Verification errors and number of cycles added. Register for frame with last RB error added. (As given by the sequence the frames are stored in the flash) Register for frame being verified added. (As given by the sequence the frames are stored in the flash.) Status register re-arranged Error register added Command register re-arranged –Clear error and clear status added. –Added Selectmap Command register –Added Flash Command register Removed delay in between scrub cycles The current frame read back is stored in memory  More sophisticated verification can be done from DCS board.