STT-RAM Feasibility Study Amr Amin UCLA Jan 2010

Outline Introduction Memory Cell Cell Area Calculation Write Current Limitations Reading Techniques and Limitations Effect of Process Variations and Mismatch MTJ Feasible Region Area Minimization

Introduction The need for a universal memory Brief history of magnetic device memories Description of the MTJ device Literature survey … Summary of the paper flow

STT-RAM Cell Schematic diagram Anti-parallelizing / Parallelizing currents Read disturb problem Cell layout Basic cell area vs. access device width

Effective Cell Area This takes into account the overhead of: –Column MUX –Row decoder –Sense Amp –I/O circuits Area optimization should also consider: –Optimum memory partitioning –Access transistor vs. column MUX areas

Write Current Limitations MOS drain current equation and fitting Maximum allowed R P and R AP for certain write current(s) Column MUX design (justification for using T-gates instead of P-transistors) Effect of each of the four MUX devices on the maximum allowed resistances

NMOS Drain Current

PMOS Drain Current

Maximum R AP

Maximum R P

Reading Limitations Current sensing Voltage sensing

Constant ‘Read’ Signal Contours Current SensingVoltage Sensing

Process Variations MOS variations: –Min K and max VT –Reduce the maximum allowed R P and R AP Mismatch: –Degrades sensitivity of the SA –Higher nominal read margin is required MTJ variations: –MgO thickness and area variations –Distort the nominal feasible region of the MTJ

Process Variations

MTJ Feasible Region What is the MTJ feasible region in the R P ­ R AP plan given the following: –Desired write current –Desired basic cell area –Column MUX width –Certain technology –Certain variations (Yield) –Matching parameters (Yield)

Dec-2009 Tape-out IBM-90nm-CMOS V WL = V DD = 1 V I WR = 500 μA W a =2.56 μm W P,MUX =16 μm W N,MUX =8 μm MOS K varies +/- 20% MOS VT varies +/- 50mV MTJ: RA = 2 Ω.μm 2 MTJ: K RA = 34 Ω.μm 2 /nm MTJ: TMR = 100% MTJ: K TMR = 200 %/nm MTJ: Δt MgO = 0.2 A o Current Sensing: V R = 600 mV Current Sensing: ΔI R = 20 μA

SRAM-Area Constraint IBM-90nm-CMOS V WL = V DD = 1 V I WR = 500 μA W a =2.56 μm W P,MUX =16 μm W N,MUX =8 μm MOS K varies +/- 20% MOS VT varies +/- 50mV MTJ: RA = 2 Ω.μm 2 MTJ: K RA = 34 Ω.μm 2 /nm MTJ: TMR = 100% MTJ: K TMR = 200 %/nm MTJ: Δt MgO = 0.2 A o Current Sensing: V R = 600 mV Current Sensing: ΔI R = 20 μA

Flash-Area Constraint

DRAM-Area Constraint

Area Minimization Problem Minimize: Effective cell area Subject to: –MTJ resistances and write current value –MTJ variations –Parallelizing/Anti-parallelizing Write current equations –MOS variations and matching parameters –Speed must come into picture to constrain the optimum memory partitioning May be able to formulate this into a standard optimization problem form that can be solved efficiently

Remaining Issues Analyzing Read/Write Speed and adding this as a constraint in the optimization problem The same with power More analysis is needed for the minimum required sensing signal (current or voltage) –CMOS mismatches and offset –Signal degradation due to MgO thickness variation –Possible signal degradation due to CMOS process variation (dependant on the SA implementation) Regenerating all results for different technologies