1. Amr Amin Preeti Mulage UCLA CKY Group
STT-RAM Test Chip #1
Weekly Status Report
Date: Wed Oct
Amr Amin Preeti Mulage
UCLA
CKY Group

2. Access Device Sharing Paths for current exist in every row
Sharing is not possible using this architecture
We are back to one access device for each cell !

3. LVT Access Transistor
Max RP and RAP for the three cells for different write currents
Low VTH
Std VTH

4. LVT Access Transistor
Max RP and RAP vs. WCELL for IWRITE = 500μA

5. Leakage Simulation Leakage vs. Number of Rows in the array
– Current design : 64 rows
Cell # 2
Cell # 3
LVT Acc Dev
LVT Acc Dev

6. MTJ Data Green cells fit in Cell #2 design space
Red cells do not fit for Cell #2
No cells fit for Cells #1 and #3

7. MTJ Design Space

8. Column MUX Sizing
Model

9. Column MUX Sizing
Simulation