1. Amr Amin Preeti Mulage UCLA CKY Group
STT-RAM Test Chip #1
Weekly Status Report
Date: Wed Oct
Amr Amin Preeti Mulage
UCLA
CKY Group

2. Top Cell Schematic Reused Blocks: Designed Blocks: Row pre-decoder
Column pre-decoder
Row Decoder
I/O buffers
Designed Blocks:
Memory array
COL MUX
Sense amp

3. Memory Array Schematic
6416 storage cells
64 2 reference cells
Need to add dummy cells

4. Memory Cell Schematic
Rmtj = 400-Ohm and 800-Ohm

5. COL MUX Schematic

6. MUX Layout Estimate
Pitch = 1.45μm
Length = 14μm

7. Sense Amp Schematic

8. Current Sense Amp Schematic

9. SA Layout Estimate
Area = 33μm  31μm (v.s. 26μm  18μm)

10. Latch Schematic

11. SRAM Layout Row DEC COL MUX Row PreDEC Sense Amps COL PreDEC
I/O Buffers
CLK GEN
COL MUX
Row DEC

12. Chip Layout Floor Plan Area estimate: Timing circuits are not included
200μm120μm
Timing circuits are not included