Front end electronics for the Tile HCAL prototype Felix Sefkow DESY CALICE Collaboration ECFA workshop Durham September 1, 2004

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 2 Outline System considerations Special SiPM requirements Front end chip Readout boards Work done at DESY, LAL, MEPhI

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 3 HCAL modules 38 layers 30 * 220 tiles 8 * 145 tiles SiPMs with coax cables ~ 8000 analogue channels in total 1 m 2 with 220 tiles Aim at common design for HCAL and tail catcher (~350 channels) SiPM

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 4 CALICE ECAL readout overview 10k analog channels From P.Dauncey

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 5 ECAL front end board 216 channels 12 lines 18x MUX From C. de La Taille

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 6 ECAL electronics scheme From C. de La Taille

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 7 ECAL DAQ CERC (CALICE ECAL r/o card) 8x12 ADCs, 8 MB memory (1-2k events) DAQ rate 1 kHz peak, 100Hz average 180 ns trigger latency 6 more HCAL boards would fit into ECAL crate From P.Dauncey

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 8 System approach The Tile HCAL has a similar number of (analogue) channels as the ECAL, distributed over a similar number of layers The two systems have to be integrated for the bulk of the testbeam program, the combined ECAL plus HCAL runs Use the ECAL electronics as starting point and adapt it to the electronic requirements of the SiPM photo detector and the HCAL mechanics

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 9 SiPM requirements Si PM signals: –gain 10 6 :1 photo electron= 160 fC –MIPs~ 25 p.e.= 4 pC –dyn range:Max signal = 400 pC –fast:few ns rise time pulse shape given by wave length shifter fibre SiPMs so far used with short gates (100 ns) and charge-integrating ADCs (“QDCs”) Noise rate is 2 MHz: a signal every 500 ns dominated by 1 pixel signals rate at kHz level with threshold at ¼ MIP but could create pile-up with slow shaping for single p.e. signals

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 10 SiPM calibration The MIP signal determines the energy scale –monitor overall response scint, SiPM, FEE LED: inject UV into scintillator: –Single photon peak spacing :non-linearity correction (together with MIP and universal response function) gain monitoring: SiPM temperature sensitivity: Gain: 3%/K, Signal: 4%/K –Medium LED signals: stability between MIP calibration runs –Large LED signals: direct non- linearity monitoring Charge injection: electronics calibration a must!

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 11 Fast shaping tests with SiPM minical cassette at LAL, Orsay 26ns peaking time

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 12 Slow shaping Checked: No problem for MIP 110 ns peaking time ~60 ns

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 13 Unipolar shaping Tests done at MEPhI combine FLC_PHY1 preamp with external shaping amp avoiding long undershoot also minimizes pile-up Figure 1.4 shaper output From B.Dolgoshein

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 14 2 SiPM FEE Proposals Unipolar shaping –as shown by MEPhI measurements, this should allow to perform single pixel gain calibration and data taking with same shaping time –Need two different gain settings Two different shaping times (and gains) –for LED calibration can delay pulse, not constraint to 150 ns –take LED runs more often than MIP data –relate two scales by LED at ~MIP amplitude validate with “fast” triggered MIPs –requires short LED pulses to obtain MIP shape from WLS Both simulated, both implemented in chip prototype (LAL)

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 15 Front end chip 100n F 10pF Variable Gain Charge Preamplifier Variable Shaper CR- RC² 12kΩ 4kΩ 24pF 12pF 3pF in 8pF4pF2pF1pF 40kΩ 8-bit DAC 1-5V ASIC 5kΩ 50Ω 100MΩ 2.4pF 1.2pF 0.6pF 0.3pF 0.1pF 0.2pF 0.4pF 0.8pF 6pF Test_pulse Technology: AMS 0.8  m CMOS From L.Raux

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 16 Flexible pulse shaping Calibration mode –Single photoelectron response –Cf=0.2pF ; τ =12ns –1 spe = 8.9 mV ; tp=40 ns –Noise : 720 µV rms Physics mode –MIP (=16pe) response –Cf=0.4pF ; Rc=5k ; τ =120ns –Gain = 12 mV/MIP ; tp=186ns –Noise = 570 µV rms –Cf=0.4pF; Rc=0 ; τ =180ns –Gain =14mV/MIP ; tp=150ns –Noise = 220 µV –Swing voltage: ~2.5V From L.Raux

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 17 Unipolar path 5pF Vref 5.5pF OTA Gm=1uA/V 3.5kΩ 7kΩ 11pF 2.8kΩ Calib switch 1 MIP response * MIP response 1 pe response 1 MIP=16pe response From L.Raux

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 18 Bias voltage scheme Requires “HV” on shield of coax cable We assume we can work with 12 HV channels: 40, 43,…,73V, max 4 available on one cassette input 50Ω 100nF SiPM 100kΩ 100nF 8-bit DAC ASIC From L.Raux, modification FS

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 19 Front end PCB ? 38x 216 coax cables in One cable (64 pin mini-SCSI) to DAQ: –13 analogue (12 out, 1 in) –19 digital (5 out, 14 in: CLOCK, HOLD, ….)

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 20 Proposed HCAL front end architecture Mother board with 12 pre-amp piggy-backs and communication card amplifiers Communication To DAQ bards Cassette 1m 2 For tail catcher: (16 layers, 20 ch / layer) Use same piggy backs Use same communication card Connect piggy-backs by cables (with or w/o motherboard?) housing

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 21 Mother board and receiver card Mother board, maybe two parts –Strictly passive don’t screw anything to cassette which needs to go to the electronics workshop –4 – 6 layers –Impedance controlled lines for analogue and fast digital signals Communication card –Holds 64 pin scsi connector –LVDS to LVDS (fast), LVDS to CMOS (slow) –Analogue output driven on piggy-back only –Fan-out calibration trigger and amplitude to LED drivers on opposite side of cassette or

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 22 The piggy-backs One preamp chip FLC_SiPM –18 in, 1 out Charge injection calibration Level conversions for fast signals (CLOCK, HOLD) FLC_SiPMCalib LVDS to CMOS Analogue Driver 18x Coax 2 or 3-row connectors Cassette (12 mm) Iron (16 mm) housing

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 23 Connectors 3 rows, 2.54 mm pitch, would allow to minimize crosstalk –signal 1groundsignal 3ground… –HV 1HV 2HV 3HV 4… –signal 2groundsignal 4ground… Need to test whether really needed, since few % optical crosstalk to be tolerated anyway Need some mechanical structure for safe mounting and dismounting of connectors

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 24 Alternative proposal Mother board with 3 pre-amp piggy-backs, 4 FLC_SiPM chips each amplifiers Communication To DAQ bards Cassette 1m 2 housing Fewer connectors in total, possibly easier and safer mechanics, But Less modular, and probably only 2 row connectors feasible

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 25 Cabling Connection SiPM to coax cable –Test soldering procedure –Check for cross talk Tests being prepared as components become available –now Actual leads are shorter, Capton strips longer Leads are presently not bent before mounting SiPM

ECFA LC workshop, Durham, Sept 2004Felix Sefkow, Front end electronics for the Tile HCAL prototype 26 Conclusion A unified ECAL + HCAL readout scheme seems possible Sample-and-Hold type solutions for SiPM r/o were found and implemented We are looking forward to learn from prototype FLC_SiPM chipd (this month) First conceptual designs of readout board exists –Also to be used for tail catcher An interesting testing period ahead