1. Some aspects of the DAQ for the Tile-HCAL Prototype Volker Korbel, DESY, for the CALICE/Tile-HCAL group Montpellier, France, 13-16 November 2003 Hadr. Calorimeter HCAL Analog version: scintillator tile read-out, small tile sizes, moderate granularity Si-PM or APD as sensors MiniCal : photodetectors DAQ, Formats Physics Prototype granularity DAQ scheme trigger, rates beam time required preamps, VFE time schedule 2003/1004

2. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 2 Single looped fibre strong fibre bending, most stress on fibres, probably ageing damages? tiles, fibers, light yield Centre/straight WLS-fibreDiagonal/bent WLS-fibre No stress on fibre, fibre end reflector =tile reflector L=7,85cm L=5cm L=20cm 1.4 mm hole in centre drilled and polished For 5 cm straight WLS-fibre RO cheep, for SiPM’s only more stress on fibre, fibre end reflector =tile reflector L=7.85cm clear RO fibres: l=1-3.5m to photo detector light attenuation <18%

3. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 3 Photo-detectors “Conventional” “Direct coupling” Optical Connector + SiPM, APD WLS&SIPM ---- 2 ways: SiPM Presented and discussed in Boris Dolgoshein’s and Erika Garutti’s talks today. Si-PM’s (MEPHI/Pulsar): 1024 pixels, 1 mm 2, on tile, gain ~ 10 6 at ~ 60V U bias need low noise fast preamplifiers APD’s (Hamamatsu S8664-55spl) 3 x 3 mm 2 photo-cathodes, gain ~200 at ~ 420V U bias need charge sensitive, low noise preamplifiers Need special masks on photo-cathode for optical fibres Light yield for MIP’s (used for calibration): 18-25 ph.e. on photo-cathode

4. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 4 MiniCal array, 1. prototype Assembled with: 13 scintillator layers of 9 tiles in cassettes with 117 scintillator tiles 117 Si-PM photo-detectors: 1 tile/Si-PM 36 photodetectors: APD’s or 3 MA-PMs,16 pix. each 3 tiles/pixel E-beam Aim of these studies: with cosmics, study of: LY uniformity of response stability of MIP signals different photodetectors long term ageing calibration with MIP’s LED monitoring: stability dynamic range measurement e-beam, study of: energy resolution constant term X X X

5. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 5 MiniCal, visitors view

6. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 6 Status of DAQ (MiniCAL, I) Up to 200 ADC channels  controlled via CAMAC CAMAC crate Power Supply current limits checked  sufficient power for 22 ADC modules (2249A) synchronization of multiple ADCs at high rates (~1kHz)  PC parallel port + special TTL-NIM adapter Data Acquisition system for MiniCal:

7. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 7 Linear Collider I/O (LCIO) “persistency” framework defining a data model for LC Studies Generator geometry Analysis Recon- struction Simulation LCIO Persistency Framework Java, C++, Fortran Geant3, Geant4 Java, C++, Fortran LCIO: - I/O Format agreed upon for LC related studies -Facilitates sharing of results -Originally developed for MC purposes (Mokka/Brahms) -Recent version v00-08 contains also data entities to store real data - Frank Gaede more info  http://www-it.desy.de/~gaede Data (new) Detector

8. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 8 pad sizes, granularity, # of tiles 3, 6 and 12 cm

9. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 9 The Ppt DAQ concept APD fibre masks or flat-band connector to Si-PM cassette RO printed circuit ~ 3m analogue RO CALICE UK group, P. Dauncey 16 bit ADC‘s

10. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 10 The Ppt DAQ concept Energy measurement: 16-bit ADC’s to cover large dynamic range between MIP’s (ch. 50) and 5 GeV on cell ( ~200 x larger) Trigger: coincidence from beam- or cosmic-trigger coincidence, LED, min. bias Latency of overall trigger path < 180ns This is from peak of shaping time in VFE chip for sample-and-hold Jitter on trigger < 10ns Trigger sent after event, not before No trigger from VFE level, some delay of analogue signals Beam measurements: particle type, x-y, time, double hits in shaping time (early and late pile-up) Beam counter, rate monitoring slow controls U bias, LV, temperatures, LED settings,...

11. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 11 DAQ rates, beam time request Need high statistics for accurate simulation comparison Multiple set-ups (energy, particle type, HCAL, angle, TC, etc) ~ 10 2 Need high statistics per set-up; accurate to 3  needs ~ 10 6 events Need to take data in a reasonable time For 10 8 events total, need around ~100 Hz average >>> minimum 10 6 seconds is around two weeks continuous running time Several months realistic beam time

12. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 12 The VFE-ROB-scheme, APD’s Array of single APD’s n x 9 x 2 pulse shapers Sample & hold Multi plexer (analog) Trigger/ RO clock LED signals PIN diode for LED monitoring HV, decoupled, common value charge sensitive preamps HV, < 440 V on board  V/V~10 -5 0,03 mA/ch cosmic beam Charge injection DAC, pedestals pedestals

13. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 13 The VFE-ROB-scheme, Si-PM’s pulse shapers Sample & hold Multi plexer (analog) Trigger/ RO clock HV, decoupled Receiver + PM voltage fast preamps (gain variable ? ~10) pedestals HV on board, PC controlled ~ 60 V  V/V~10 -3 cosmic beam Charge injection DAC Variable gain,3-4 steps Signals from Si-PM‘s in calo structure

14. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 14 Sh S&H Mul PrA Orsay FLCHPY3 Dig. DATA A P D 17 (18) ADC AD7677 16 bit 1µsec/ch HV 20 Sept. VFE board development status, Dubna Input from Igor Tiapkin

15. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 15 LED test Dubna test board for CAMAC RO Ready soon for tests with CAMAC

16. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 16 R&D for Ppt, VFE prototype cards VFE-Boards with LAL/Orsay preamp chips for APD’s: LV supply multiplexed ADC RO HV-PS (500 V) LED monitoring multiplexing VFE / CAMAC RO 2 options: APD gain >200:12 mV/7.2 fC <100:12 mV/1.8 fC

17. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 17 1. Reading LAL/Orsay chip. Critical to the SH signal ±10nsec Multiplexer switching time ~100 nsec 2. ADC on board is ok. 3. Data are in CAMAC. 4. Now tests with 2 APD (and Si-PM’s) is going on. Await soon: 1.Number of channels per board? 4 FLC chips - 72 channels ADC AD7924 12bit, 4 ch, 1µsec. 100-150 µsec readout time LED test? need help from DESY for design (mechanics, exp. from H1) VME modules from UK? need readout in spring 2004 Dubna, present status

18. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 18 VFE solution for Si-PMs Have to inquire and take decision soon: fast preamps, short gates, to reduce noise collection voltage amplifier ok? fast preamp output to be gated by trigger (100-180 ns later) >>>needs: fast analogue delay lines or fast switch capacity memory downstream preamp ahead of shaping how many channels/board (5000-8000 Si-PM’s ?) U bias, ~60V, remote set of +/0.1 V steps, 10 steps?

19. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 19 Dubna, next steps Prot. test Pilot boards production Materials ? HV test If ok LED calibr. Test? NOWNOW First board Second board 2 months 1 month ? End November, HCAL main-meeting End of 2003 ? HV on board: APD ~400V generating on the board (tuning for each channel probably not needed) SI-PM’s ~60V delivering to board, tuning for each channel

20. V. Korbel, DESY, CALICEMontpellier, France, 13-16 November 2003 20 the Ppt construction program Ppt stack construction: 3 months tender and ordering 3 months to build Moving beam platform include in 6 month More APD’s to order, have 58, need 150 (200), 2 month delivery Press form for tile production: 4 months Scintillator production >> tiles: 3months Si-PMs (~5000) 3 months production, 3 months acceptance tests 2. batch (~3000) needed Acceptance tests with tiles with inserted Si-PM’s needs 3 months after production, 1. September finished Cassettes design to be fixed next 3 months, test needed All equipped cassettes could be available in end October 2004 Decision on preamps and VFE logic for Si-PM’s and APD’s in 2003 Prototype VFE board from Dubna needed spring 2004.>>>>>>>>all boards ready Sept.2004 CALICE-UK DAQ prototype ready 1. March 2004 March-August, System tests with cassettes, cosmic and DAQ at DESY, need increasing quantities of cassettes Ppt e-beam test with ECAL at DESY in October 2004