1 Status Report on ADC LPC Clermont-Ferrand Laurent ROYER, Samuel MANEN Calice/Eudet electronic meeting London 2008

10/01/2008 VFE electronics of Si-W Ecal 2 Calice/Eudet electronic meeting London 2008 Requirements for ILC –Ultra low power: 25µW/ch for the whole Very-Front-End electronics, including ADC –Resolution of ADC: 10 bits if 3-gain shaping 12 bits if 2-gain shaping –Compactness, electronics embedded in detector Three main LPC 1.10-bit Pipeline ADC: tested and measured 2.12-bit Wilkinson ADC: mature enough to be implemented in SKIROC 3.12-bit Cyclic ADC: new challenge

10/01/2008 1) A 10-bit 5V pipeline ADC 3 Calice/Eudet electronic meeting London 2008

10/01/20084 Calice/Eudet electronic meeting London 2008 Mettre vue du schéma skiroc avec ADC Main performance of the10-bit pipeline ADC  Performance measured:  Effective Resolution of 10 bits with limited INL & DNL  Noise (including the setup noise): σ < 0.5 LSB  Consumption: 35 mW/5V  Conversion time: 0.25 µs 4MHz) NonLinearity (measured): Integral NL LSB Differential NL LSB

10/01/2008 A 10-bit pipeline ADC for Calice 5 Calice/Eudet electronic meeting London 2008 Publication submitted to IEEE-Nuclear Sc.

10/01/2008 2) A 12-bit 3.5V Wilkinson ADC 6 Calice/Eudet electronic meeting London 2008

10/01/20087c Calice/Eudet electronic meeting London 2008  Characteristics:  Techno: BiCMOS SiGe 0.35µm  Power consumption: 3 3.5V  Power pulsing  Conversion time :  Differential architecture  Open loop ramp generator  Die area: 0.12 mm 2 12-bit Wilkinson ADC in SKIROC Layout of the ADC One channel SKIROC diagram ADC/LPC

10/01/2008 SKIROC LPC 8 Calice/Eudet electronic meeting London 2008 Comparator signal Analog signal in SCA SC1SC2 SC3 SC4 SC5 t1t3t2t4t5 Status:  One test board given by LPC to test ADCs  LabView Control program developed by LAL used to configure SKIROC through USB interface  Several bugs found in the digital part (in FPGA)  Fixed by LAL  ADC functionality checked with scope

10/01/2008 SKIROC LPC 9 Calice/Eudet electronic meeting London 2008 Analog signal on SCA USB Pulse signal on SKIROC input ADC SKIROC chip LAL test boardLPC test board Remote Pulse generator Setup to test the (preampli + shaper) linearity  To measure ADC performance, the automatic transfer of the ADC digital data from FPGA to PC via USB is required  under LAL  We have adapted the setup of the test LPC to measure linearity of the analog channel (preamp + shaper) and to compare results with those LAL

10/01/2008 Linearity LAL 10 Calice/Eudet electronic meeting London 2008 Not expected saturation 1200 MIPs

10/01/2008 Linearity LPC 11 Calice/Eudet electronic meeting London 2008 Shaper: Gain 1

10/01/2008 Linearity LPC 12 Calice/Eudet electronic meeting London 2008 Same saturation LAL &LPC: >>> not induced by the test bench

10/01/2008 3) A 12-bit 3.5V Cyclic ADC 13 Calice/Eudet electronic meeting London 2008

10/01/ Calice/Eudet electronic meeting London 2008 Objective : –Design a 12-bit cyclic ADC with 3.5V power sup. based on the buildings blocks of the pipeline ADC but with a lower power supply (5V  3.5V) –Gain 2 accuracy required for a 12-bit ADC is multiplied by 4 compare to a 10-bit ADC 10 bits ADC accuracy is 1/ bits ADC accuracy is 1/4000 Two chips designed to characterize two main elements of 12-bit cyclic ADC –Comparator (July 06) –Gain-2 amplifier (July 07) 12 bits – 3.5V cyclic ADC

10/01/ Calice/Eudet electronic meeting London 2008 Comparator measurements Characteristics:  Technology: CMOS 0.35µm  Power supply: 3V  Clock frequency: 10 MHz  Differential architecture  Consumption: 68µA  7 chips tested Max. Sensitivity: 3 ±3  including setup noise  Requirement: < 0.5 mV Measurements must be improved OK in simulation Max. Offset: 10 mV  Requirement: < ± 125 mV 10 mV Offset measurements Sensitivity measurements 3 mV 0 mV Dominated by setup noise

10/01/ Calice/Eudet electronic meeting London 2008 Gain-2 amplifier: preliminary results  Technology: CMOS 0.35µm  Power supply: 3.5V  Differential architecture  Consumption: 2.8 mW  Gain : 16 k  Gain Band product: 50 MHz  Linear, Stable  Matching of capacitors optimized (precision of gain 2) Characteristics & performance: 10-bit version amplifier New 12-bit version amplifier Systematic error introduced by test bench ±1LSB

10/01/2008 Simulation of the 12-bit cyclic ADC 17 Calice/Eudet electronic meeting London 2008  An original architecture:  One gain-2 amplifier and two comparators required  Only 6 periods of clock needed to achieve a conversion  Simulated performance:  Integral Non-Linearity nearly within ±1 LSB  Conversion time (clock freq. of 1MHz) : 6 µs  Power consumption: 3.2 mW Integral Non-Linearity (simulated)

10/01/2008 Summary 18 Calice/Eudet electronic meeting London 2008 # bitsPrecision Integ. consum. per channel Die areaStatus Pipeline 1010 bits 0.22 µW (1%) 1 ADC/n channels 1.4mm 2 Tested & publicated Wilkinson low energy 10 high energy 6 µW (13%) 1 ADC/channel 0.12mm 2 in SKIROC Test in progress Cyclic 1212 bits  0.5 µW (2%) 1 ADC/channel  0.15 mm 2 in develop t Building blocks validated  Our Wilkinson ADC is a candidate for the EUDET VFE chip… IF its performance is confirmed by measurements  Our cyclic ADC, which is an evolution of the pipeline ADC, should be a good candidate to the final chip (accurated, low power, compact…)  Fabrication and test of prototypes foreseen in 2008

10/01/2008 SPARE SLIDES 19 Calice/Eudet electronic meeting London 2008

10/01/ Calice/Eudet electronic meeting London 2008 Performance of the10-bit pipeline ADC Measured noise (including the setup noise): σ < 0.5 LSB INL with rms noise Codes code center (512)

10/01/2008 Linearity measurements 21 Calice/Eudet electronic meeting London 2008 Channel 1 & 2 Shaper: Gain 1

10/01/2008 Results 22 Calice/Eudet electronic meeting London 2008 Channel 2 & generator

10/01/ Calice/Eudet electronic meeting London 2008

10/01/ Calice/Eudet electronic meeting London 2008

10/01/ Calice/Eudet electronic meeting London 2008