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Signal Digitization Issues for the NLC Muon Detector Mani Tripathi UC, Davis 8/5/03 Starting Point: 1.Time of arrival measurement with O(1 ns) resolution.

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Presentation on theme: "Signal Digitization Issues for the NLC Muon Detector Mani Tripathi UC, Davis 8/5/03 Starting Point: 1.Time of arrival measurement with O(1 ns) resolution."— Presentation transcript:

1 Signal Digitization Issues for the NLC Muon Detector Mani Tripathi UC, Davis 8/5/03 Starting Point: 1.Time of arrival measurement with O(1 ns) resolution. 2.Pulse height measurement with O(10 bit) resolution. These were the preliminary conclusions of an email discussion. I will assume for this talk that pulse-shape recording with O(1 Gsps) is desirable if it also achieves the above goals.

2 Signal Considerations Single p.e. Response: Using the typical gain and rise-time characteristics and a triangular approximation, 1 p.e. = [(4 x 10 6 ) * (1.6x10 -19 C)/(0.6 ns)] *(50  ) = 530 mV Preamp response (gain of 8) = 4 V @ a rise-time of 0.6 ns = 1 V @ a rise-time of 2.4 ns (preliminary – please check the numbers)

3 Amplifier Response OUTPUT INPUT The amplifier reproduces the input pulse shape faithfully => the inherent rise-time of the amplifier is better than 1 ns.

4 Digitization with Effective10-bits Variable Splitter High Gain Output (1 p.e. = 400 mV) Low Gain Output (1 p.e. = 25 mV) The dynamic range of the digitizers is 800 mV, which will imply 2 p.e. in the top channel and 30 p.e in the bottom channel. (note -- not clear if it is +- 400mV or 800 mV single-ended without adding a DC bias.) The preamp gain may have to be reduced to achieve these rations -- Of course, these ratios are easily changeable by the User. 6-bit 800 MHz Flash ADC

5 ADC Selection chart (Maxim-IC) The highlighted part is 1) fast enough, 2) has 2 channels, 3) larger dynamic range of 800 mV And 4) has an LVDS output which makes it easier to interface with FPGAs. It is only 6-bits and not 8-bits but much cheaper (cost for 8-bit versions is >$100/channel).

6 ADC Selection (Contd.) There is a 10-bit model available but it will not have adequate time-of-arrival resolution.

7 Summary A board with a simple splitter system and dual channel ADCs can be developed. 16 channels per board can be accommodated. Interfacing is an open question – We prefer USB because of simplicity. The implementation will most likely be via an FPGA The cost per channel in large quantities will be ~ $50. The cost for development of prototype board will be of the order $ 20 K.


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