Backplanes for Analog Modular Cameras EVO meeting. March 14 th,

Backplane functionalities Power supply for the front-end boards, the PMTs and the backplane itself. Clock distribution. Analog Trigger. Digital Trigger. Calibration. Data transfer. Compatibility with camera structure. Compatibility of interfaces. 2

Power supply requirements Front-end boards need ± 3.3V (Nectar & Dragon). PMTs require + 5V (Dragon Japan), or + 12V (Nectar). PMTs require HV ?? (Dragon Italy). L0 fanout requires ± 3.3 V in the backplane. Others? 3

Power supply alternative 1 Backplane receives +12 V and has DC/DC converters to obtain +3.3, -3.3 and +5 V. – Supplies the front-end with +12, and +5 V. – Only one power cable per cluster, with +12V – It needs at least 4 input pins to the front-end board for power. – Simpler front-end boards. – Difficult to develop the backplane: little space, a lot of noise which can disturb analog signals. 4

Power supply alternative 2 Backplane receives +12 V, some DC/DC are placed in the backplanes and others in the front-end boards. – Backplane simpler than with alt. 1, but still noisy. – Complex and potentially noisier front-end boards. – Less power pins between backplane and front-end  In fact, only + 5V is required at front-end, as backplanes also need V ??? – Only one power cable per cluster, with +12 V 5

Power supply alternative 3 Backplane receives +12V, +5V, +3.3V and -3.3V from a central power supply. – Simple backplanes. – Simple front-ends. – Less switching noise than alt. 1 and 2 – More cables (4 per cluster, although they could be routed together). – More dissipation and less energetic efficiency. – Complex central power supply. 6

Other power supply issues Is it possible to place the central power supply at the base of the telescope? – Camera would be lighter and with less heat dissipation. – It would be possible to use complex and heavy linear power supplies, completely avoiding switching noise. – Less efficient, losses in the cables. Not very important if dissipation is outside the camera. – Cables are also heavy, but the extra weight would be distributed through the structure. Is it possible to share the power supply among neighbor clusters? – Loops? 7

Clock Distribution Dragon requires central fast clock distribution and 1 PPS(EXTCLK and TIME signals?) Nectar only need 1 PPS signal (EXTCLK?) For high accuracy (<1 ns) APC clock distribution provides: – 1 PPS – 10 MHz clock (if required by the DAQ) – One trigger copy to the central clock unit of the camera – One sync signal to the digital trigger distribution system. If not so much accuracy is required (5 ns), analog trigger distribution system is also able to distribute the clock. It also requires 1 PPS and 10 MHz clock input signals, in the backplane of central cluster. 8

Analog Trigger 1.Front-end to back-plane 1 L0 analog differential output (L0_OUT). 1 differential analog L0 input from the cluster itself (L1_IN1). 2 LVDS digital outputs from the L1 (L1_OUT and L1_OUT2), to be able to implement Region-of-Interest (Colibri-like). Otherwise, only one is required. 1 LVDS differential digital input from the distribution to the DAQ FPGA, which effectively triggers the cluster (L1A). 4 digital lines between the distribution board FPGA and the DAQ FPGA, for slow control (bidirectional SPI). 2.Back-plane to neighboring back-plane 5 differential analog L0 outputs to the neighbors (CL2 to CL6). 5 differential analog L0 inputs from the neighbors (L1_IN2 to L1_IN4, L1_IN6 and 7). 12 LVDS digital outputs to distribute L1_OUT and L1_OUT2 to the neighbors. 12 LVDS digital inputs to receive L1_OUT and L1_OUT2 from the neighbors. 9

Digital Trigger Analog trigger backplane will not implement digital trigger, but it is very interesting to have the same interface between the front-ends (Nectar/Dragon) and the backplanes (analog/digital). 8 digital input differential pairs (TRG_INP0 to TRG_INP7). 7 digital output differential pairs (TRG_OUT0 to TRG_OUT6) 1 digital differential pair TRGL1 1 digital differential pair TRGCONF EXTCLK TIME 10 Mhz clock and 1PPS ?? 10

Calibration signals One digital line from the DAQ FPGA to configure a backplane state in which L1 does not receive L0 inputs from the neighbors, but only from its own cluster. This makes possible to calibrate the analog trigger delays of all the clusters in the camera at the same time. One LVDS trigger reference to calibrate analog trigger delays. Provided by the L1 distribution in the backplane, to the front-end board. One LVDS software trigger pair. It can be the same lines as the ones used for calibrating the analog trigger delays. Others? 11

Data Transfer One Ethernet connector is required to read the data (pairs MD0 to MD3). 12

Compatibility with camera structure The backplane design is strongly constricted by the camera structure: – One backplane per cluster, or is it possible to make a backplane for seven clusters in a single board? – Is available space for backplanes already fixed? What shape? Is there any mechanical obstacle? – Available height for connectors? – The connector between the backplane and the front- end boards must allow a reliable connection of the clusters from the front side of the camera. – How much weight for cables? A common repository of 3D mechanical models or blueprints is desirable. 13

Compatibility of interfaces One large connector between the backplane and the front-end boards with: – 4 power supply voltages – 2 differential pairs for clock distribution (1PPS and 10 MHz) – 1 analog differential pair for L0 output – 6 analog differential pairs for L1 inputs – 2 LVDS pairs for L1 outputs – 1 LVDS pair for L1 distribution input – 4 single ended digital lines for L1 distribution board FPGA slow control. – 8 input differential pairs for digital trigger – 7 output differential pairs for digital trigger – 1 digital differential pair TRGL1, for digital trigger – 1 digital differential pair TRGCONF, for digital trigger – 1 digital single ended line to select calibration mode in the backplane. – 2 LVDS pairs for delay calibration and software trigger – 4 differential pairs for Ethernet data transfer 35 differential pairs + 5 single-ended lines + power supply The connector also must comply with mechanical constrains! Or two connectors: one for signals and another for power supply ? 14

Compatibility of interfaces Six connectors from every cluster to its neighbors. The lines in this connectors will be different depending on the selected trigger scheme (digital or analog trigger backplanes). For the analog backplane, each connector will have: – 1 L0 output analog differential pair – 1 L0 input analog differential pair – 2 L1 LVDS outputs – 2 L1 LVDS inputs – 10 MHz and 1PPS pairs if distributing the clock with the L1 distribution hardware. For the digital trigger analog backplane: ? 15

Compatibility of interfaces One Ethernet connector for data transfer. Other RJ45 connector for clock distribution: – 1 LVDS pair for 10 MHz clock – 1 LVDS pair for 1 PPS – 1 LVDS pair from digital trigger distribution to Central Clock – 1 LVDS pair from Central Clock to digital trigger distribution One or more power supply connectors Other dedicated connector for calibration signals (time reference, software trigger), at least for analog trigger central cluster? Probably it is possible to do this reusing the RJ45 dedicated to clock distribution, sending different messages. 16

Possible common features with FlashCam Power supply. Data transfer. ? 17

Next steps Requirements document: – Writers – Deadline Face-to-face meeting – Date – Contents Others? 18