H.Mathez– VLSI-FPGA-PCB Lyon– June , 2012 CSA avec reset pour s-CMS, bruit en temporel (Up-Grade TRACKER) (Asic R&D Version 1)

H.Mathez– VLSI-FPGA-PCB Lyon– June , CSA Requirements  Qin = 1.2 fC to 10 fC (7.5 ke-, 62 ke-)  Charge Collection Time = 10ns  Cd = 5pF  Power supply < 200 µW/amplifier  F_slhc = 20 Mhz (version 1) or 40 Mhz  Output pulse < 50ns  S/N = 20 (before irradiation)  ENC = 700 e- if Q = e- = 2.4 fC (before irradiation) Q is the most probable value for a Landau distribution of input charge  S/N = 10 (after irradiation)  ENC = 700 e- if Q = 7500 e- = 1.2 fC (after irradiation)  Front-End in AC coupling mode

H.Mathez– VLSI-FPGA-PCB Lyon– June , Schematic - Power Supply 115µA 10µA Idet X10 10µA  IBM 130nm Process  Power supply 1.6V  NMOS input transistor : 143 µA (including bias current)  Bias current cascode : 28 µA  SF output : 200 µA  CSA Power Supply 171 µA (274 µW) compared to 253 µW in schematic simulation

H.Mathez– VLSI-FPGA-PCB Lyon– June , Noise in a Non Switched CSA Cd - + Cf Votage Noise Current Noise Rf Rf is a noiseless resistor G0  0 : GBW of amplifier Equation 1 Equation 2

H.Mathez– VLSI-FPGA-PCB Lyon– June , Noise in Switched CSA Cd - + Cf Votage Noise Current Noise  Using the weighting function (F S Goulding NIMA )  Noise is measured just before the reset switch on Voltage noise is independent of switching time Current noise is proportional to the switching time If Strips are AC coupled Voltage noise is dominant whereas in DC coupled both (en and in) contribute to the output noise G0  0 : GBW of amplifier loaded by Cd and Cf Equation 3Equation 4

H.Mathez– VLSI-FPGA-PCB Lyon– June , KTC noise Rf Cd - + Cf Votage Noise Switched closed : at the end of Reset noise is stored in Cf or in Cd+Cf Ideal amplifier (G=∞,  0=∞): no noise stored in Cd and v 2 =kT/Cf is transferred to the output during readout Poor amplifier : noise is stored on both Cf and Cd and v 2 =kT/(Cf+cd) will be amplified during readout

H.Mathez– VLSI-FPGA-PCB Lyon– June , KTC noise Bandwidth amplifier > Bandwidth Ron*Cf (1/RonCf) Bandwidth amplifier < Bandwidth RonCf Ron=100Ω, G0=57dB, f0=1GHz

H.Mathez– VLSI-FPGA-PCB Lyon– June , Noise simulation (AC noise) has been made for 2 different Rf in non switched CSA, i n and e n can be extracted Ouput noise is the sum of equation 1 and equation 2 K1 = 73.8E9 K2 = 2.5E12 (Cf = 0.1pF) i n 2 = 5.85E-28 A 2 /Hz e n 2 = 8.3E-18 V 2 /Hz i n = 24.2 fA/sqrtHz (eq 1.88 nA shot noise) e n = 2.88 nV/sqrtHz ( eq 500  resistor) V out, noise 2 = 760 nV RF1 100 M  V out, noise 2 = 615 nV RF2 1 M  (760 nV 2, Vout=74 mV, Qin=10fC ~ ENC = 730e-) Eq 1 and 2 V out, noise 2 (en) = 612 nV RF1 100 M  V out, noise 2 (in) = 146 nV RF2 100 M  e n is dominant noise source Noise calculation Noise simulation in AC mode and calculation for switched mode

H.Mathez– VLSI-FPGA-PCB Lyon– June , Noise calculation in switched mode using : e n (computed in previous slide) i n (computed in previous slide) equation 3 and 4 V out, noise 2 (e n ) = 610 nV 2 V out, noise 2 (i n ) = 340 pV 2 Total output noise = 610 nV 2 = 780 µV Vout = 74 mV ENC = 658 e- Tr_noise simulation : 200 iterations Fmax = 5GHz Vout 26 ns Compute the standard deviation for all values 26ns Total output noise = 738 µV Vout = 74 mV ENC = 623 e- 2 ways to simulate noise in switched CSA: TR_noise Standard AC noise + calculation Noise calculation Calculation and TR_noise simulation in good agreement TR_noise: No noise summary More CPU time More reliable AC Noise: Increase by 20% of noise Noise summary available Less CPU time

H.Mathez– VLSI-FPGA-PCB Lyon– June , Vout vs cd Input capacitor : Cd : 4.9 pF C(Cd + PCB + test socket) : 9 pF C(QFN package) : 0.5pF Cesd input pad : 2pF Total input capacitor : 12.5pF mV fC Tin = 40ns Gconv = 6.3 mV/fC (In agreement with test 6.2 mV/fC))

H.Mathez– VLSI-FPGA-PCB Lyon– June , ENC vs Cd (AC noise simulation) ENC (5pF, 100 M  ) = 730e- ENC (15pF, 100 M  ) = 1260e- 5pF < Cd < 15 pF 730e- 1260e- 26ns Vout for ENC calculation Vout = 74mV Output Noise = 871µV Vout = 70mV Output Noise = 1.41mV

H.Mathez– VLSI-FPGA-PCB Lyon– June , ENC vs Cd (TR noise simulation) Cd = 5pF Cd = 15 pF Tin = 26 ns, simulation time 50ns, 100 iterations 674e- 1363e- 25 ns for ENC calculation Vout = 55mV Output Noise = 1.2mV Vout = 71mV Output Noise = 766µV

H.Mathez– VLSI-FPGA-PCB Lyon– June , Cd = 5pF Vout = 77 mV Stddev = 1.25 mV ENC = 1014 e- Cd = 12.5pF Vout = 64 mV Stddev = 1.59 mV ENC = 1552 e- ENC vs Cd (TR noise simulation) Tin = 26 ns, simulation time 10µs, 200 pulses Cd = 5pF Cd = 15 pF

H.Mathez– VLSI-FPGA-PCB Lyon– June , ENC vs Cd (TR noise simulation) Cd = 12.5pF Vout = 67 mV Stddev = 1.62 mV ENC = 1511 e- Tin = 40 ns

H.Mathez– VLSI-FPGA-PCB Lyon– June ,  Fclk = 15 MHz  Asic 3 Reset CSA Output CSA RMS Noise = 1.32 mV  1600 e- Tests Results - Noise Qin = 0 Qin = 1.2 fC Output Signal Dispersion 2 histograms lightly 15 MHz S/N = 7.5 (compared to 10 required) MIP : 1.2 fC CSA RMS Noise = 1.32 mV  1600 e- Cd ~ 12.5pF (5 pf in simulation) ENC for 5pf will be 1600/sqrt(2.5) = e-

H.Mathez– VLSI-FPGA-PCB Lyon– June , ENC Fclk = 15 Mhz (Tin = 40 ns) ASIC ASIC ASIC ENC in 15 Mhz ENC (simulated 12.5pF = 1140 e- ENC (simulated TR noise n pulses, Tin = 26ns, sim time 12.5pF = 1080e- ENC (simulated TR noise, Tin = 26ns, sim time 12.5pF = 1552e- ENC (simulated TR noise Tin 12.5pF = 1511 e-

H.Mathez– VLSI-FPGA-PCB Lyon– June , Conclusion CSA works 15 Mhz Step in progess :  increase performance (Speed, S/N, 40 MHz Clocking)  ASIC with few channels (CSA, Comparators) : possible submission fall 2012  Both sensor polarities (holes or electrons)  1.2 v & low temperature