1. LEPSI ir e s MIMOSA 13 Minimum Ionising particle Metal Oxyde Semi-conductor Active pixel sensor GSI Meeting, Darmstadt Sébastien HEINI 10/03/2005

2. LEPSI ir e s Summary - Charge sensing element : PhotoFET. - Readout in current mode - MIMOSA 13 : a highly granular and fast sensor. - Conclusion and outlook. Sébastien HEINI 10/03/2005

3. LEPSI ir e s PhotoFET : charge sensing element - The collected charge affects the threshold voltage of the PMOS transistor - Modulation of the transistor current  signal amplification resulting in conversion of the generated charge to current Advantages: - Built-in charge-to-current amplification -high sensitivity -Large DC swing -High speed readout Sébastien HEINI 10/03/2005 - 100% fill factor - N-WELL/P-epi Diode. - Liberated Charge ~80e - /µm/MIP - Collection time ~100ns

4. LEPSI ir e s Optimal operation point and result of the PhotoFET Optimal running S/N point determined by simulation. -Isf_ bias = 1µA - Signal = 773 pA / e - - Noise = 49 e - - S/N = 34 - 1M events analysis. - Blue curve : neighbour pixel hit response distribution analysis - Green curve : calibration pick due to a Fe55 X ray irradiation on the central pixel - Signal / noise depend on neighbour pixel hit ADC count Number of pixels Sébastien HEINI 10/03/2005

5. LEPSI ir e s Current mode readout Sébastien HEINI 10/03/2005 Advantages: -High speed readout. -Charge collected is amplified inside the pixel. -Low impedance is in the amplifier (outside of the array). -Pixel output simple : using a current memory. -Large DC swing.

6. LEPSI ir e s Objective of MIMOSA 13 - High gain sensing element. - DC current compensation. - Noise reduction of the PhotoFET structure. - AC coupling test for lower noise contribution. - Obtain a readout time faster than 100ns. - Direct access to the PhotoFET for caracterisation. - Test of a real fast amplifier architecture. (readout time faster than 50ns). - Test of the chip MIMOSA 13 in fast operation mode. - Pixel array 20 x 64 (pixel pitch 20µm). - Compatibility with datas acquisition of existing system. Sébastien HEINI 10/03/2005

7. LEPSI ir e s MIMOSA 13 Topology - Technology : AMS 035. - (4 metal layer). - Substrate : low doped Hi resistivity substrate (8-10 Ω.cm). - Chip Area : 5,1mm² - Nb of pads : 44 - Pads spacing : 50µm - Gnd : 4 - Digital : 11 - Vdd : 1 - Out : 10 - Selection : 3 - Bias : 8 - Vdda pixel : 4 - Vdda ampli : 2 Sébastien HEINI 10/03/2005

8. LEPSI ir e s Global view of MIMOSA 13 architecture ………………………................................. Parallel readout row Pixels Array DIG. bloc ………………… Amplifier PhotoFET Reaout line : metal wire memory Sébastien HEINI 10/03/2005 Current output Column

9. LEPSI ir e s MIMOSA 13 Pixels Array (New PhotoFET) Pixel A1 10 x 16 10 Sorties analogique I Pixel A2 10 x 16 Pixel A3 10 x 16 Pixel A4 10 x 16 Pixel B2 10 x 16 Pixel B1 10 x 16 Pixel B3 10 x 16 Pixel B4 10 x 16 10 Sorties analogique I Dummi Pixel : Mimosa 7 photofet pixel to solve process continuity problems Pixel A1 : Mimosa7 avec Photofet pixel, new layout. Pixel A2 : Modified Photofet, source follower bandwith limitation, memory W/L=3 + cap, Photofet with W/L=3. Pixel B1 : Pixel with Pmos transistor and AC coupling, Current mirror reference and compensation, memoiry W/L=3 + cap. Matrice de Mosaic 2 : 64 rows of 20 pixels (20 x 20µm pitch). Successive row readout Sébastien HEINI 10/03/2005 Pixel A3 : Modified Photofet, source follower bandwith limitation, memory W/L=3 + cap, Photofet with W/L=2,2. Pixel A4 : Modified Photofet, source follower bandwith limitation, memory W/L=2 + cap, Photofet with W/L=2,2. Pixel B4 : Pixel with Pmos transistor and AC coupling Nmos cap, High gain, directe reference and compensation, memoiry W/L=3 + cap. Pixel B3 : Pixel with Pmos transistor and AC coupling Nmos cap, directe reference and compensation, memoiry W/L=3 + cap. Pixel B2 : Pixel with Pmos transistor and AC coupling gate cap, directe reference and compensation, memoiry W/L=3 + cap.

10. LEPSI ir e s MIMOSA 13 Array - 6 x 64 command lines. - Successive row readout - Write and read pattern is equal for all the pixels (A1 …B4). -100ns for the memory writing. - 100ns for the readout of the memory SW_PWON OUT SW_W_M1 SW_W_M2 SW_R_M1 SW_R_M2 SW_R_PH VDDA_SFVDDA_PHFET BIAS_pixel Pixel GND  -------- 100ns -------  Sébastien HEINI 10/03/2005

11. LEPSI ir e s Pixel structure SW_PWON Pixel OUT SW_W_M1 SW_W_M2 SW_R_M1 SW_R_M2 SW_R_PH Current memory 1 Current memory 2 Photofet Charge sensing element PIXEL Sébastien HEINI 10/03/2005 - Signal is contain in noise –Fixe Pattern Noise –Electronic noise – (thermal, 1/f, shot noise) - Signal is extract using (CDS) correlated double sampling -S1 t1, S2 t2  Signal = S1 - S2

12. LEPSI ir e s Amplifier and multiplexer structure Sel amp Sel dir Bias A1 Bias A2 Sel 1_2 Dc current Compensation bloc Analog multiplexer 10 input analog I 10 output analog I Classic amplifier, gain 10 Fast amplifier Ampli Analog output Mux 2 vers 1 Ampli Bias_comp Sébastien HEINI 10/03/2005

13. LEPSI ir e s Conclusion and outlook Current mode maybe adapted to the high speed and high granularity requirements. Most of the design is realized. Submission on 25 march 2005. Sébastien HEINI 10/03/2005 Design of the test bench for MIMOSA 13. Test and analysis of MIMOSA 13 chip. Work over an fast ADC flash for analog signal conversion.

14. LEPSI ir e s Pixel type A1, A2, A3, A4 - 6 commandes : Sw_pwon Sw_r_ph Sw_w_m1 Sw_w_m2 Sw_r_m1 Sébastien HEINI 10/03/2005

15. LEPSI ir e s Pixel type B1 - 6 commandes : Sw_r_ph Sw_w_m1 Sw_w_m2 Sw_r_m1 Sébastien HEINI 10/03/2005

16. LEPSI ir e s Pixel type B2, B3, B4 - 6 commandes : Sw_r_ph Sw_w_m1 Sw_w_m2 Sw_r_m1 Sébastien HEINI 10/03/2005

17. LEPSI ir e s Bloc d’amplification gain 10 Sébastien HEINI 10/03/2005

18. LEPSI ir e s Bloc d’amplification rapide Sébastien HEINI 10/03/2005