1. ITRS-2001 Joint Meeting Design ITWG / USA Design TWG February 4, 2001 SF Marriott, Pacific G, 4pm-10pm PST Dial-in: 888-422-7124, Participant Code 672208

2. Agenda - Part I Summary of previous ITWG/TWG meetings [15m] Hiwatashi-san ITWG System Drivers Chapter [2 hrs, 4:15-6:15pm] Outline 5 min Andrew Kahng Introductory material –Market Drivers 15 min Don Cottrell (phone) SOC example section 20 min Res Saleh Power roadmap 20 min Shekhar Borkar, Bora Nikolic Discussion 60 min –tables, figures, metrics (some general, some driver-specific) –assignment of sections (HVC, SOC, DRAM, AMS/RF) »proposal: HVC (uP, DSP etc.) = USA, AMS/RF = Europe, SOC (low power, fast TTM etc.) = Japan (what about DRAM?) –overall review of chapter (does it work?) –ARs for Grenoble and beyond

3. Agenda - Part II Design Chapter [2.25 hrs, 6:15-8:30pm] Outline 5 min Andrew Kahng Columns 50 min »Design Process - Don Cottrell; System-Level Design Herman Schmit; Functional Verification Carl Pixley; Logical-Physical- Circuit Andrew Kahng / Res Saleh; Test Justin Harlow / Tim Cheng Core Tables (Tables X) 40 min »AMSRF - Al Dunlop / John Cohn / Rick Carley, and Ralf Brederlow; ASIC/SOC - Res Saleh / John Darringer / Andrew Kahng; HVC - Peter Bannon; DRAM - ? »Mixed-signal roadmap »STRJ Design Report on Low Power and DSM Issues Discussion 40 min –Discussion of chapter organization, tables, figures –Metrics (design process, design productivity) Peter Bannon / ? –Untouched issues (Introduction, Design Cost,...) –Text-writing assignments –ARs for Grenoble and beyond

4. Agenda - Part III ORTCs and Other Interactions [1.5hrs, 8:30-10pm] SRAM and Logic A factors 20 min Dennis Sylvester / Jeff Davis Clock Frequency and Power 20 min Peter Bannon / Mark Horowitz Package Pins/Ball 20 min Dennis Sylvester / Andrew Kahng Other –study groups (chip size, global interconnect, system cost) –TWGs (PIDS, Interconnect, Litho, FEP, Assembly/Packaging, Test) Discussion –ARs for Grenoble and beyond

5. Agenda - Part I Summary of previous ITWG/TWG meetings [15m] Hiwatashi-san ITWG System Drivers Chapter [2 hrs, 4:15-6:15pm] Outline 5 min Andrew Kahng Introductory material –Market Drivers 15 min Don Cottrell (phone) SOC example section 20 min Res Saleh Power roadmap 20 min Shekhar Borkar, Bora Nikolic Discussion 60 min –tables, figures, metrics (some general, some driver-specific) –assignment of sections (HVC, SOC, DRAM, AMS/RF) »proposal: HVC (uP, DSP etc.) = USA, AMS/RF = Europe, SOC (low power, fast TTM etc.) = Japan (what about DRAM?) –overall review of chapter (does it work?) –ARs for Grenoble and beyond

6. This shows how ORTCs and System Drivers should form the “glue” to unite all other chapters.

7. Proposed rough outline of System Drivers chapter. If the SOC template is agreeable, then we can try to distribute the effort across regions (we also need input from other TWGs). E.g., DRAM - Korea, ASIC/SOC - Japan, AMS/RF - Europe, HVC - US.

8. This was a worked exercise to answer Bill Joyner’s questions for a given section in the System Drivers chapter. I.e., What does X drive? What is driven by X? “Factors” break down into “objectives” (which drive particular system driver classes) and “consequences/phenomena” (which are demanded by particular system driver classes). This actually looks like an unrolled directed bipartite graph ({classes} X {factors}). Perhaps we can use such a figure in the Intro of the System Drivers chapter.

9. Agenda - Part II Design Chapter [2.25 hrs, 6:15-8:30pm] Outline 5 min Andrew Kahng Columns 50 min »Design Process - Don Cottrell; System-Level Design Herman Schmit; Functional Verification Carl Pixley; Logical-Physical- Circuit Andrew Kahng / Res Saleh; Test Justin Harlow / Tim Cheng Core Tables (Tables X) 40 min »AMSRF - Al Dunlop / John Cohn / Rick Carley, and Ralf Brederlow; ASIC/SOC - Res Saleh / John Darringer / Andrew Kahng; HVC - Peter Bannon; DRAM - ? »Mixed-signal roadmap »STRJ Design Report on Low Power and DSM Issues Discussion 40 min –Discussion of chapter organization, tables, figures –Metrics (design process, design productivity) Peter Bannon / ? –Untouched issues (Introduction, Design Cost,...) –Text-writing assignments –ARs for Grenoble and beyond

10. Chapter Organization - Mapping “Context” Scope of Design Technology High-level summary of complexities (at level of “issues”) (Andrew, JohnD, Bill) Cost, productivity, quality, and other metrics of Design Technology (Ted, others TBD) Overview of Needs Driver classes and associated emphases (Don, Steve, Gary) Resulting needs (e.g., power, …, cost-driven design) (Jeff, Dennis, Res + AMS/RF (AMS/Circuits group) + SOC (Ted/Randy?) + uP (Mark, Peter) + ASIC (?)) Summary of Difficult Challenges (All) Detailed Statements of Needs, Potential Solutions (All) Silicon (Physical, Synth/Logic, AMS/Circuits, Verif/Analysis groups) System (Test, Verification (digital, analog), System-Level groups) Design Process (Methodology/Metrics group)

11. Design chapter outline. Needs intro. Where should cost be discussed ? as part of Design Process ?

12. Core Figures and Tables - 1999 List: –Table 4 – Issues taxonomy (+) –Figure 5 – Design Productivity Gap (-) –Figure 6 – Evolution of Design System Architecture (++) –Figure 7 – Superexponential Complexity (--) –Table 13 – Difficult Challenges (++) –Table 14 – Requirements (Metrics) (-, should be +) –Figure 8 – Allocation of Verification Effort ( ? Should do this for all Design Effort ? ) –Figure 9 – Increase in Test Time ( ? ) –Figure 10 – MOS f_T, f_max ( ? ) –Figure 11 – Half-perimeter Delay vs. Core Size ( ? ) Comments: uneven, sometimes not very “concrete”

13. Core Figures and Tables - 2001 List: –Table – Issues taxonomy –Table – Metrics of Design Technology –Figure – Evolution of Design System Architecture –Figure – “Business Design Driver” Classes –Table(s) – Design Difficult Challenges (???) What does this look like ? –Additional Figures, Tables within the Detailed Statements of Needs and Potential Solutions sections Silicon System Design Process

14. Table X: Specific Design Challenges for Microprocessor Drivers near-term (>100nm) long-term (<100nm) criticality Design Process System-Level Design Functional Verification Logic/Phys/ Circuits Test *** have a graph like this for SOC, Analog/RF, and ASIC?? system only challenge #1 cross-cutting challenge between logic and system#1 cross-cutting challenge between systems, logic, circuit, PD, and system system only challenge #1 Logic only challenge #1 system only challenge #1 circuit only challenge #1 system only challenge #1

15. Table X: Top Design Cross-cutting Challenges for System Drivers (Near-Term) criticality SOCAnaloguProcASIC cross-cutting challenge between SOC and Analog #1 cross-cutting challenge between SOC, Analog SOC Challenge Only Logic only challenge #1 system only challenge #1 circuit only challenge #1

16. COMMENTS Comment re memory content of SOC (Gary Smith, 010202): “We are fairly steady at 33% of the chip in memory. In fact large blocks of memory seem to be dying off in high end designs. They are going to large number of memory instances to increase performance and decrease power consumption along the lines of what Hugo and IMEC have been preaching recently.” Comment re analog roadmap (John Cohn, Rick Carley, Al Dunlop, 010202):

17. Agenda - Part III ORTCs and Other Interactions [1.5hrs, 8:30-10pm] SRAM and Logic A factors 20 min Dennis Sylvester / Jeff Davis Clock Frequency and Power 20 min Peter Bannon / Mark Horowitz Package Pins/Ball 20 min Dennis Sylvester / Andrew Kahng Other –study groups (chip size, global interconnect, system cost) –TWGs (PIDS, Interconnect, Litho, FEP, Assembly/Packaging, Test) Discussion –ARs for Grenoble and beyond