Presentation on theme: "Winter Public Conference ORTC 2010 Update"— Presentation transcript:
1Winter Public Conference ORTC 2010 Update A. Allan, Rev 2, 12/02/10
2450mm timing presently unchanged from 2009 ITRS position IRC 2010 Update Messages:450mm timing presently unchanged from 2009 ITRS positionHowever, FI will extend 300mm wafer generation in parallel line item header with 450mm; andEmphasize compatibility of productivity extensions into the 450mm generation;FI update also indicates that its activities are relevant to legacy wafer generations (e.g. MtM technologies)More than Moore white paper final ITWG draft is completed and available onlineNew “Moore’s Law and More” Graphic update proposal for the 2011 ITRS Executive Summary RenewalThe 2010 ITWG work is based on frozen 2009 HeadersTechnology Pacing focus issues identified and addressed (see Technology Pacing agenda Foil)Beyond CMOS –Research tools and material (pre-alpha material and tool) timing needs to be taken into accountPIDS and ERD and ERM are coordinating new technology transfers (e.g. InGaAs; Ge) for 2011 ITRS work Kickoff proposalsESH shifting focus to future material use and risk mitigation (living “white paper” proposed) on ITRS forum siteIRC 2010 Summary special topicsEnergy topic UpdatedERD/ERM Next Memory Storage Spring Meeting completed 3rd conference in Japan at Winter meetingTechnology Pacing CTSG proposals are integrated into PIDS Tables and ORTC Table1 at Dec’10 Japan Workshop for the 2011 ITRS Executive Summary RenewalEquivalent scaling graphic update for the 2011 ITRS Executive Summary RenewalParallel bulk and SOI pathwaysClarification of gate mobility materials pathwayComparison alignment with ITRS dimensional vs. industry typical “node” trends
3IRC/CTSG Winter 2010 Technology Pacing Cross-TWG Study Group (CTSG) Agenda: IRC/Technology Pacing CTSG TOPICS - CTSG 2010 Proposals consideredDuring Winter Meeting 2011 Renewal work from 2H10 CTSG Discussions:PIDS and FEP Memory Survey Proposal Updates - to be used for 2011 RenewalFEP and Design and System Drivers – will investigate MPU and Leading Edge Logic technology trend proposals for 2011 RenewalPlus Continued 1Q11 CTSG 2011 Renewal work on:Litho – develop proposals utilizing # of Mask layers inputs [see ICKnowledge (ICK) contribution in backup]Design/Interconnect - Andrew/Juan-Antonio/Chris Case - reconciled the Interconnect and Design Tables alignment issuesA&P/Design - Bill Bottoms/Andrew/Juan-Antonio – work on proposals for reconciling the Power Dissipation (absolute "hot spot" basis rather than total chip area for 2011 RenewalPIDS/Design – work on 2011 Renewal proposals forNew Max Chip Frequency trends (lower model basis plus long term trend)Changes to the 13% PIDS Overhead trend vs. new Design Max Chip Frequency trends;Updates regarding ring-oscillator basis;Timing changes to “equivalent scaling” tradeoffs with dimensional scalingORTC model update proposals added from work in 2H10 CTSG work for 2011 Renewal
4Figure 4 The Concept of Moore’s Law and More 2010 ITRS Summary Figure 4Figure 4 The Concept of Moore’s Law and MoreMore than Moore: DiversificationMore Moore: MiniaturizationCombining SoC and SiP: Higher Value SystemsBaseline CMOS: CPU, Memory, LogicBiochipsSensorsActuatorsHVPowerAnalog/RFPassives130nm90nm65nm45nm32nm22nm16 nm.VInformationProcessingDigital contentSystem-on-chip(SoC)Beyond CMOSInteracting with people and environmentNon-digital contentSystem-in-package(SiP)
52010- Update Flash Poly Definition 2009 Definition of the Half Pitch – New Poly Definition[No single-product “node” designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables]Source: ITRS - Exec. Summary Fig 1PolyPitchTypical flashUn-contacted PolyFLASH Poly Silicon ½ Pitch= Flash Poly Pitch/28-16 Lines LinesMetalTypical DRAM/MPU/ASICMetal Bit LineDRAM ½ Pitch= DRAM Metal Pitch/2MPU/ASIC M1 ½ Pitch= MPU/ASIC M1 Pitch/2
6Structure (electrostatic control) 2010 ITRS Summary Figure 3 “Equivalent Scaling” RoadmapFigure 3 ORTC Table 1 Graphical Trends (including overlay of 2009 industry logic “nodes”and ITRS trends for comparison)Updated Proposal for 2011 work [from 11/11 CTSG; 11/15 IRC telecon]MetalHigh kGate-stack material20092012201520182021BulkFDSOIMulti-gate(on bulk or SOI)Structure (electrostatic control)Channelmaterial2nd generationSi + StressSDHigh-µInGaAs; Ge; ?PDSOInth generationPossibleDelayPossible Pull -in6See also PIDS, FEP, ERD, and ERM chapters’ text and tables for additional detail)68nm45nm32nm22nm16nm2009 IS ITRS DRAM M1 :2009 ITRS MPU/hpASIC M1 : 76nm 65nm 54nm 45nm 38nm 32nm 27nm nm nmMPU/hpASIC “Node”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”2009 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm2009 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm11nm2009 IS ITRS Flash Poly :54nm2009 ITWG Table Timing:= Additional timing movementconsiderations for 2011 ITRS work
72010 Update ITRS ORTC Technology Trend Pre-Summary ORTC Model Proposals to TWGs for TWG Interdependency Preparation for other ORTC section features:“Equivalent Scaling” timing unchanged in 2010 for ERD/ERM early research and transfer to PIDS; however need for continued discussion about transfer of alternative Gate Material technology in 2011 RenewalLogic “Equivalent Scaling” Roadmap Timing Update underway, and ongoing discussion of alignment of “node” and dimensional Trends for 2011 RenewalNew “More than Moore” (MtM) white paper completed for 2011 ITRS Renewal impact and added to the ITRS website atMPU contacted M1Unchanged for 2010 [validated by FEP data]2-year cycle trend through 2013Cross-over DRAM M1 2010/45nmSmaller 60f2 SRAM 6t cell Design FactorSmaller 175f2 Logic Gate 4t Design FactorTwo proposals [2011 Renewal work]: for Design TWG to evaluate possible 1-year M1 delay (IC TWG: two companies not meeting roadmap); and also evaluate alignment of “nodes” with latest M1 industry status and also High Performance/Low Power timing needs (Taiwan IRC request)DRAM contacted M1Unchanged for 2010: Dimensional M1 half-pitch trends remain unchanged from 2007/08/09 ITRS; new 4f2 Design factor begins 2011Proposal [2011 Renewal work]: 1-year pull-in of M1 and bits/chip trends to end of roadmap*; 4f2 push out [to 2013]; *no Flattening of DRAM M1 as with Flash Poly**Flash Un-contacted PolyUnchanged for 2010: 2yr cycle trend through 2010/32nm; then 3yr cycle and also added “equivalent scaling” bit design:Inserted 3bits/cell MLC ; and delayed 4bits/cell (2 companies in production) until 2012Proposal #1[2011 Renewal work]: year pull-in of Poly; however slower ~4-year cycle trend to 2015/18nm; then 3-year trend to 2022; ** then Flat Poly after 2022/8nm; and 3bits/cell extended to 2018; 4bits/cell delay to 2019Additional Proposal consideration underway for 2011 Renewal due to recent announcements
82010 Update ITRS ORTC Technology Trend Pre-Summary (cont.) 5) Unchanged for 2010 Tables: MPU GLpr – ’08-’09 2-yr flat; Low operating and standby line items track changesUnchanged for 2010 Tables: MPU GLph – ’08-’09 2-yr flat with equiv. scaling process tradeoffs; Low operating and standby line items track changesPerformance targets (speed, power) on track with tradeoffs7) Primarily Unchanged [corrections to Intro Level product line items – see backup] for 2010 Tables: MPU Functions/Chip and Chip Size ModelsUtilized Design TWG Model for Chip Size and Density Model trends – tied to technology cycle timing trends and updated cell design factorsORTC line item OverHead (OH) area model, includes non-active areaORTC model impact updating from PIDS/FEP Survey proposals evaluation underway for 2011 Renewal]DRAM Bits/Chip and Chip Size Model Unchanged for 2010 Tables - 3-year generation “Moore’s Law” doubling cycle;smaller Chip Sizes (<60mm2) with 4f2 design factor includedFlash Bits/Chip and Chip Size Model Unchanged for 2010 Tables2-year generation “Moore’s Law” doubling cycle;growing Chip Sizes after return to 3-year technology cycleIRC 450mm Position: Pilot lines/2012; Production/ Unchanged for 2010; also Unchanged: “double S-curve” graphic in 2010 Update Summary450mm Program status and Long-Range IEM v12 Demand Update Scenario was presented by ISMI to IRC for 2011 ITRS Renewal preparationISMI is pursuing 450mm program activities to meet the ITRS TimingEvaluation of possible impact of a delayed scenario is underway for 2011 ITRS Renewal preparation
9Figure 1 ORTC Table 1 with PIDS update proposals for 2011 ITRS effort) 2010 ITRS Summary Figure 1Figure 1 ORTC Table 1 with PIDS update proposals for 2011 ITRS effort)[including PIDS 2011 Roadmap Flash and DRAM Trend Driver Proposals]Note: additional proposals for 2011 ITRS work are under consideration due to recent additional industry technology implementation acceleration announcements. Updates will be delivered at public meetings in 2011.
102010 ITRS Summary Figure 2Figure 2 ORTC Table 1 Graphical Trends (including overlay of PIDS update proposals for 2011 ITRS effort)16nmNear-TermLong-TermPIDS DRAM Projection~1-yr pull-in42nm M1 to 2010 (2 co’s);Then 3-yr cycle to 2024/8nm;PIDS Flash Projection~2-yr pull-in26nm Poly half-pitch to 2010 (2 co’s);Then ~4-yr cycle to 2020/10nm;Then 3-year cycle to 2022/8nm;Then flat2019: PIDS Flash 4 bits/cell push-outMemoryPIDS 2011Proposals2013: PIDS DRAM 4f2 Design Factor bits/cell push-outSource: ITRS - Executive Summary Fig 7a
11Figure 5a DRAM and Flash Memory Half Pitch Trends 2010 ITRS Summary Figure 5aFigure 5a DRAM and Flash Memory Half Pitch Trends16nmNear-TermLong-TermSource: ITRS - Executive Summary Fig 7a
142010 ITRS Summary Figure 7aFigure 7a ITRS Product Technology Trends: Memory Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends
152010 ITRS Summary Figure 7bFigure 7b ITRS Product Technology Trends: MPU Product Functions/Chip and Industry Average “Moore’s Law” and Chip Size Trends2011: “22nm”/(38nm M1)MPU Model Generations
16Volume Development Production 2010 ITRS Summary Figure 8Figure 8 A Typical Wafer Generation Pilot Line and Production “Ramp” Curve applied to Forecast TimingTargets of the 450 mm Wafer GenerationVolumeYearsAlphaToolBetaTools forPilot line32nm (extendable to 22nm) M1 half-pitch capable Beta tools by end of 2011Consortium Pilot LineManufacturing22nm (extendable to 16nm) M1 half-pitch capable toolsDevelopmentProduction450mm 32nm M1 half-pitchPilot Line Ramp2010201120122013201420152016
172010 Winter Meeting Public Conference Backup ITRS “S-curves” Ramp Timing definitionERD/ERM “Beyond CMOS” Definition GraphicORTC Table 2D correctionsSICAS Capacity Analysis Graphics 60nm Split-out Analysis UpdateTypical Industry “Node” Tracking vs ITRS Technology TrendsWork in Progress – Do Not Publish!
18Production Ramp-up Model and Technology Cycle Timing 2009 WAS UnchangedProduction Ramp-up Model and Technology/Cycle TimingMonths-24AlphaTool1224-12DevelopmentProductionBetaFirstConf.PapersFirst Two CompaniesReaching Production2202002K20K200KAdditionalLead-time:ERD/ERMResearch andPIDS TransferVolume (Wafers/Month)Production Ramp-up Model and Technology Cycle Timing*Examples: 25Kwspm ~=280mm2140mm2100mm270mm2Source: ITRS - Exec. Summary Fig 2aWork in Progress – Do Not Publish!
19Work in Progress – Do Not Publish! ERD/ERM Long-Range R&D and PIDS Transfer Timing Model Technology Cycle Timing[Example: MOSFET High-mobility Channel Replacement Materials]Source: ITRS - Executive Summary Fig 2bMonthsAlphaToolDevelopmentProductionBetaProductVolume (Wafers/Month)2202002K20K200KResearch-7224-48-24-96Transfer to PIDS/FEP(96-72moLeadtime)FirstTech. Conf.Device PapersUp to ~12yrsPrior to Product201920172015201320112021Hi-mExample:1st 2 Co’sReachCircuits PapersUp to ~ 5yrs2009 WAS UnchangedWork in Progress – Do Not Publish!19
202008 ITRS “Beyond CMOS” Definition Graphic [2009 – Unchanged]2008 ITRS “Beyond CMOS” Definition GraphicComputing and Data Storage Beyond CMOSSource: Emerging Research Device Working Group“More Moore”“Beyond CMOS”22nm16nm11nm8nmBaselineCMOSUltimatelyScaled CMOSFunctionallyEnhanced CMOSSpin LogicDevicesNanowireElectronicsFerromagneticLogic Devices32nmChannel Replacement MaterialsLow Dimensional Materials ChannelsMultiple gate MOSFETsNew State VariableNew Data RepresentationNew DevicesNew Data ProcessingAlgorithmsWork in Progress – Do Not Publish!
21Work in Progress – Do Not Publish! ORTC Table 2D - Including CorrectionsWork in Progress – Do Not Publish!
22Work in Progress – Do Not Publish! ORTC Table 2C - Including CorrectionsWork in Progress – Do Not Publish!
234Q09 SICAS Update Proposal Work in Progress – Do Not Publish! From Furukawa-san/JapanTo IRC 3/28/10 (modified by AA)Technology Cycle Timing Compared to Actual Wafer Production Technology Capacity Distribution>0.7mmmmmmmmmmmm<0.08mmmm<0.06mmFeature Size (Half Pitch) (mm)= 2003/04 ITRS DRAM Contacted M1 Half-Pitch Actual= 2007/09 ITRS DRAM Contacted M1 Half-Pitch Target= 2009 ITRS Flash Un-contacted Poly Half Pitch Target= 2009 ITRS MPU/hpASIC Contacted M1 Half-Pitch Target3-Year Cycle2008/09 ITRS: 2.5-Year Ave Cycle for DRAM3-Year CycleAfter 2010 forFlash; after 2013For MPU2-Year DRAM Cycle3-Year DRAM Cycle ; 2-year Cycle Flash and MPUYearYear20102013* Note: The wafer production capacity data are plotted from the SICAS* 4Q data for each year, except 2Q data for 2009. The width of each of the production capacity bars corresponds to the MOS IC production start silicon area for that rangeof the feature size (y-axis). Data are based upon capacity if fully utilized.Source: ITRS - Executive Summary Fig 3Work in Progress – Do Not Publish!
24Industry “Node”* Alignment w/ITRS [2009 ITRS] MPU Perform/Power “Equiv. Scaling”:CopperStrainHiK/MG I, IIFDSOIMUGFET; SiGEHi-u tbdTBDDRAM Density “Equiv. Scaling”:8f26f24f2Flash Density MLC “Equiv. Scaling”:16/11/8/5.5/4f2: 2b/cell2.0f2: 2b/cell1.5f2: 3b/cell1.0f2:4b/cellDimensional Half Pitch Scaling (EOT not shown):2009 ITRS:Past Future2.57.5‘17‘16‘18‘20‘19‘21‘25‘23‘22‘24‘10‘08‘06‘04‘02‘12‘00‘14‘11‘13‘99‘01‘03‘05‘07‘09‘15YearHi-PerformanceMPU/hpASICPublic NodeReferences*;+extrapolation54~Actual76107151214382721303649012718032241925545“Node”“65”“90”“130”“45”“180”“32”“22”“16”->“8.0”“5.6”“4.0”“11”“28”“40”“55”“80”“110”“160”“20”52DRAM Actual M168901191574032252075978103136362822180451611838Flash Actual Poly5476107151282218207456490127252016180321186’01-’03: 200mm->300mm@ 180nm->130nm M1’14-’16: 300mm->450mm@ 32nm->22nm M1’91-’93: <200mm ->200mm@ 0.5u->0.35u M1Industry Typical “Node” vs ITRS M1 and Poly Alignment2009 ITWG Table Timing: ]68nm45nm32nm22nm16nm2009 IS ITRS DRAM M1 :2009 ITRS MPU/hpASIC M1 : nm 65nm 54nm 45nm 38nm 32nm 27nm nm nmMPU/hpASIC “Node*”: “45nm” “32nm” “22nm” “16nm” “11nm” “8nm”2009 ITRS hi-perf GLph : nm 29nm 29nm 27nm 24nm 22nm 20nm nm nm2009 ITRS hi-perf GLpr : nm 47nm 47nm 41nm 35nm 31nm 28nm nm nm11nm2009 IS ITRS Flash Poly :54nm2) hpASIC reference TSMC “Nodes” Articles: ;1) MPU reference: Mark Bohr Tutorial, Jul’09:*Notes on “Nodes”: DRAM, Flash “Nodes” ~= M1 and Poly Half-pitch.However high performance Logic (MPU, hpASIC) may have node “labels” Associated with their dimensional technology progress, as referenced in:MPU & ASIC Low-Power versions typically lag Gate Length to manage power and performance trade-offs at the same M1-based density “Node” as high-performance versions