1. Work in Progress --- Not for Publication 1 ERD WG 12/06/08 & 12/14/08 2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting Jim Hutchby - Facilitating San Francisco Hilton & Towers Hotel Franciscan A Room San Francisco, CA Sunday Dec 14, 2008 8:00 a.m. – 5:30 p.m.

2. Work in Progress --- Not for Publication 2 ERD WG 12/06/08 & 12/14/08 2009 ITRS Emerging Research Devices Working Group Face-to-Face Meeting U-In Chung & Jim Hutchby - Facilitating COEX InterContinental Hotel Room Moderato I Seoul, Korea Saturday Dec 6, 2008 9:00 – 17:30

3. Work in Progress --- Not for Publication 3 ERD WG 12/06/08 & 12/14/08  Hiroyugi AkinagaAIST  Tetsuya AsaiHokkaido U.  Yuji AwanoFujitsu  George BourianoffIntel  Michel BrillouetCEA/LETI  Joe BrewerU. Florida  John CarruthersPSU  Ralph CavinSRC  U-In ChungSamsung  Byung Jin ChoKAIST  Sung Woong ChungHynix  Shamik DasMitre  Erik DeBenedictisSNL  Simon Deleonibus LETI  Kristin De MeyerIMEC  Michael FrankAMD  Christian GamratCEA  Mike GarnerIntel  Dan HammerstromPSU  Wilfried HaenschIBM  Tsuyoshi HasegawaNIMS  Shigenori HayashiMatsushita  Dan HerrSRC  Toshiro HiramotoU. Tokyo  Matsuo HidakaISTEK  Jim HutchbySRC  Adrian IonescuETH  Kohei ItohKeio U.  Kiyoshi KawabataRenesas Tech  Seiichiro KawamuraSelete  Rick KiehlU. Minn  Suhwan KimSeoul Nation U.  Hyoungjoon KimSamsung  Atsuhiro KinoshitaToshiba  Dae-Hong KoYonsei U.  Hiroshi KotakiSharp  Atsuhiro KinoshitaToshiba  Franz KreuplQimonda  Nety KrishnaAMAT  Zoran KrivokapicAMD  Phil KuekesHP  Jong-Ho LeeKyungpook Nation U.  Lou LomeIDA  Hiroshi MizutaU. Southampton  Murali Muraldihar Freescale  Fumiyuki NiheiNEC  Ferdinand PeperNICT  Yaw ObengNIST  Dave RobertsAir Products  Kaushal SinghAMAT  Sadas ShankarIntel  Satoshi SugaharaTokyo Tech  Shin-ichi TakagiU. Tokyo  Ken UchidaToshiba  Yasuo WadaToyo U.  Rainer WaserRWTH A  Franz Widdershoven NXP  Jeff WelserNRI/IBM  Philip WongStanford U.  Kojiro YagamiSony  David YehSRC/TI  In-Seok YeoSamsung  In-K YooSAIT  Peter ZeitzoffFreescale  Yuegang ZhangLLLab  Victor ZhirnovSRC Emerging Research Devices Working Group

4. Work in Progress --- Not for Publication 4 ERD WG 12/06/08 & 12/14/08 Emerging Research Devices Working Group Dec. 6 th Seoul FxF Meeting Objectives  Meet with Korean ERD Working Group (Morning)  Discuss International Collaboration Processes in 2009  ERD-Korean WG Inputs  2007 Chapter Review – any Issues?  2009 Scope and Content of Chapter  Other topics?  Meet with ERM (Afternoon)  Discuss ERM/ERD Interfaces & Collaboration in 2009  Review Proposed Materials & Device Topics for 2009  Discuss III-V and Ge Channel Replacement Materials?  Discuss new Potential Solutions section on “Carbon-based Nanoelectronics”  Devices in ERD-PIDs transition table - any entries limited by materials?

5. Work in Progress --- Not for Publication 5 ERD WG 12/06/08 & 12/14/08 Emerging Research Devices Working Group Dec. 6 nd Seoul FxF Meeting – Morning Agenda 9:00Welcome and IntroductionsDrs. U-In Chung & J. Hutchby 9:15Organization of Korean ERD & Dr. U-In Chung Proposals from each part 9:20 ERD Logic part Prof. Jong-Ho Lee 9:50 ERD Memory part Dr. In-Seok Yeo 10:20 Break 10:50 ERD Architecture part Prof. Soo-Hwan Kim 11:20 Emerging Research Materials Prof. Dae-Hong Ko 12:00Lunch

6. Work in Progress --- Not for Publication 6 ERD WG 12/06/08 & 12/14/08 ERD/ERM Working Groups Joint Meeting Dec. 6 th Seoul FxF Meeting – Afternoon Agenda 13:15 Review Arch’ture Approaches & IssuesTBA 13:45 Review Memory Device IssuesTBA/V. Zhirnov 14:30 Review Logic Device IssuesG. Bourianoff 15:15 Break 15:30 Review/summarize ERM Workshops M. Garner ♦Workshops ♦ERM Tables 16:30 Review Carbon-based NanoelectronicM. Garner materials issues 17:00 Review proposed interaction with ERD M. Garner and Working GroupJ. Hutchby 17:30 Adjourn

7. Work in Progress --- Not for Publication 7 ERD WG 12/06/08 & 12/14/08  Review Feedback on 2007 ERD Chapter  Review ERD Chapter Organization for 2009  Leadership  Mission and Scope  Deliverables, Timeline and Events  Chapter page count and page allocation  Operating Process and Meetings  Technology Entries Inclusion Criteria  Broadly inclusive  Maturity Metric (current publications) Kick off 2009 ITRS ERD Chapter Preparation Dec. 14 th San Francisco FxF Meeting Objectives

8. Work in Progress --- Not for Publication 8 ERD WG 12/06/08 & 12/14/08  Review ERD Chapter Content for 2009  Major Technical Sections  Architectures  Logic Devices  Selected Emerging Technologies  Compliment or Extend CMOS  Beyond CMOS  Potential Solutions  Memory Devices  Selected Emerging Technologies  Selected Potential Solutions  Critical Review and Guiding Principle Sections  Critical Review  Selected Memory Devices  Selected Logic Devices  Guiding Principles  Review ERD Decisions & Action Items for 2009 Kick off 2009 ITRS ERD Chapter Preparation Dec. 14 th San Francisco FxF Meeting Objectives

9. Work in Progress --- Not for Publication 9 ERD WG 12/06/08 & 12/14/08 7:30 Continental Breakfast 8:00 Introductions 8:10 Review meeting objectives and agenda J. Hutchby 8:20 Review ERD Organization for 2009J. Hutchby  Leadership  Mission/Charter and Scope  Deliverables, Timeline, and Events  Chapter Page Count and Page Allocation  Operating Process and Meetings 9:00 Review status of ERDJ. Hutchby  Chapter Status & Organization  2007 ERD Chapter Feedback (12/07)  Decisions for 2009 10:00Break Kick off 2009 ITRS ERD Chapter Preparation Dec. 14 th San Francisco FxF Meeting Agenda

10. Work in Progress --- Not for Publication 10 ERD WG 12/06/08 & 12/14/08 10:15Review ERD Workshops and Discuss Status of Materials, Devices & Architectures  10:15 MaterialsM. Garner  11:00 Memory DevicesV. Zhirnov 12:15Lunch (Continue Discussion)  12:45 Logic DevicesG. Bourianoff  Complement or extend CMOS  Beyond CMOS  2:15 ArchitecturesR. Cavin 3:15Break 3:30Discuss Critical Review & Guiding Principle Sections  3:30 Critical Review J Hutchby  Memory Devices  Logic Devices  4:30 Guiding Principles J. Hutchby 5:00Wrap up, Review Decisions and Actions RequiredJ. Hutchby 5:30Adjourn Kick off 2009 ITRS ERD Chapter Preparation Dec. 14 th San Francisco FxF Meeting Agenda

11. Work in Progress --- Not for Publication 11 ERD WG 12/06/08 & 12/14/08 Mission/Charter of ERD Chapter On behalf of the 2009 ITRS, develop an Emerging Research Devices chapter to --  Critically assess suitability and maturity of novel approaches/technologies for Information Processing technology intended to complement or extend ultimate CMOS  Identify the most promising approach(es) to Information Processing technology to be implemented by 2022 To offer substantive input and guidance to –  Global research community  Relevant government agencies  Technology managers  Suppliers

12. Work in Progress --- Not for Publication 12 ERD WG 12/06/08 & 12/14/08 Scope of ERD Chapter Integrated emerging research memory, logic and new architecture technologies enabled by supporting --  Materials and process technologies  Modeling and simulation  Metrologies Technology Entries will be selected based on level of published research activity, credibility and progress  Should show significant maturity in research domain  Further adoption limited by research issues

13. Work in Progress --- Not for Publication 13 ERD WG 12/06/08 & 12/14/08 Scope of ERD Chapter Criteria for Including Technology Entries Research Devices and Architectures –  Published by 2 or more groups in archival literature and peer reviewed conferences, or  Published extensively by 1 group in archival literature and peer reviewed conferences

14. Work in Progress --- Not for Publication 14 ERD WG 12/06/08 & 12/14/08 Scope of ERD Chapter Fundamental Requirements for CMOS Extension Information Processing Technologies  Provides a valuable macro function more efficiently than CMOS  Energy restorative process (e.g. gain)  Functionally interfaceable with CMOS  At or above room temperature operation  Minimum energy per functional operation  Minimum, scalable cost per function

15. Work in Progress --- Not for Publication 15 ERD WG 12/06/08 & 12/14/08 Scope of ERD Chapter Fundamental Requirements for Beyond CMOS Information Processing Technology Entries  Information processing throughput orders of magnitude beyond ultimately scaled CMOS  Energy restorative process (e.g. gain)  Functionally compatible with CMOS  At or above room temperature operation  Reduced energy per functional operation  Reduced, scalable cost per function

16. Work in Progress --- Not for Publication 16 ERD WG 12/06/08 & 12/14/08 Proposed 2009 ERD Working Group Organization ERD FunctionLeader u Chapter Chair – North AmericaHutchby u Chapter Co-chair – EuropeTBD u Chapter Co-chair – Japan ERDHiramoto u Chapter Co-chair – Korea ERDChung u MemoryZhirnov u LogicBourianoff u ArchitectureCavin u Editorial TeamHutchby, Bourianoff, Cavin, Chung, Garner/Herr, Hiramoto, Zhirnov u ITRS Liaisons –PIDSNg, Hutchby –FEPHerr –Modeling & SimulationShankar –MaterialsShankar –MetrologyHerr –DesignYeh/Bourianoff –More than MooreBrillouet

17. Work in Progress --- Not for Publication 17 ERD WG 12/06/08 & 12/14/08 2009 ITRS/ERD Major Deliverables and Timeline ERD Chapter due August 21, 2009 Major Tasks and Time Line  Outlines for Memory, Logic, Architecture, Mat’lMarch 18  Technology Requirements TablesApril 6  Guiding Principles Section June 1  Draft Text Completed  Memory, Logic, Architecture, MaterialJuly 6  Functional Organization & Critical ReviewJuly 20  Scope, Difficult Challenges, etc.July 27  Chapter CompletedAugust 21  Chapter FrozenSept. 15 Major Face-to-Face Meetings in 2009  ITRS/ERD Meeting near Brussels, BelgiumMarch 18  ITRS/ERD Meeting at Semicon West (SF, CA)July 12  ITRS/ERD Meeting near Hsinchu, TaiwanNov. 30

18. Work in Progress --- Not for Publication 18 ERD WG 12/06/08 & 12/14/08 2008 ERD/ERM Workshops Done

19. Work in Progress --- Not for Publication 19 ERD WG 12/06/08 & 12/14/08 Draft ERD Chapter Outline  Scope (1 page)  Difficult Challenges (1)  Taxonomy Chart (1)  Devices  Memory Devices (15)  Logic Devices (15)  Architectures (8)  Critical Assessment (6)  Fundamental Guiding Principles (3)  Total Pages (50) DRAFT

20. Work in Progress --- Not for Publication 20 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Overall Comments  Increase involvement of international members – strengthen ties between US – EU – Asia. Requires good balance of representing members from these three regions.  Mission of ERD is not clear cut to universities – clearly state the mission in the introduction.  Need more detailed discussion of key messages and issues between ERD and ERM  To what extent and how does ERD/ERM deal with More than Moore?  Need a metric to gauge the potential of each Technology Entry to be disruptive.  Is a Technology Entry being limited by Fundamental Limits or a technologically limited research gap?  ERD needs to maintain a dialog with the Systems Drivers Chapter  Should ERD continue to include a failing Technology Entry?

21. Work in Progress --- Not for Publication 21 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Emerging Research Memory Devices ♦ Transfers  Engineered Tunnel Barrier Memory to PIDS and FEP  Keep the Ferroelectric FET Memory Technology in ERD  Include STT RAM as a new entry. Given progress, should we include STT RAM in a new Potential Solution Table for Memory Technologies? ♦ Other comments  Re-combine the capacitive and resistive memory tables  Discuss other materials (in addition to Pt/NiO/Pt) for Fuse/Anti-fuse Memory  Try to elucidate fundamental limits of Memory Devices  Add a new row to memory table to include Storage Capacity  Address Memory Architecture, perhaps in the Architecture Section  Why do all the memory technology entries have for “Best Projected Write Cycles” a value of 3E16 ?  Include scaling projections for all Memory Technology Entries  The Memory Group is preparing a single reference document containing scaling projections and citations

22. Work in Progress --- Not for Publication 22 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Emerging Research Logic Devices (1/3) ♦ Transfers proposed  III-V Alternate Channel Materials to PIDS/FEP and  Low Dimensional Materials to PIDS/FEP  Move Molecular Devices to the Transition Table.  Include Band-to-Band Tunneling Device category in Table 1.  Move RTD out of Table 2 to Transition Table ♦ Other comments  The comprehensive review with references is important  Like having two tables to represent the traditional, digital Boolean device applications and the new table to represent new, perhaps analog, applications of emerging research devices.  Include chart entitled “Evolution of Extended CMOS” from Japan ERD  The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect.  Define “Switching Speed” and “Circuit Speed”

23. Work in Progress --- Not for Publication 23 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Emerging Research Logic Devices (2/3) ♦ Other comments  Discuss “Spin Gain Transistor” and “Spin Torque Transistor” in text. “Single Spin device” is not in the table  Should we constrain Logic Technology by availability of Memory Tech?  Should use term “high mobility/high velocity” instead of “high mobility”  Improve linkages to the Architecture Section and to the System Drivers Chapter.  Increase emphasis on Table 2 while maintaining Table 1. Place a stronger emphasis on non-linear response functions. Think about how to amend Table 1 to differentiate “Beyond CMOS” devices.  Separate Spin FETs from Spin State Devices (Spin transport without charge transport) and evaluate as separate categories.  Divide Table 1 into 2 tables – one for CMOS extension and the other for Beyond CMOS?  Include Spin Wave Bus in Table 1?

24. Work in Progress --- Not for Publication 24 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Emerging Research Logic Devices (3/3) ♦ Other comments  Keep SETs in Table 2, Alternative Information Processing Technologies  Change Multiferroic Tunnel Junction Devices to Multiferroic Switching Device and keep in Table 2.

25. Work in Progress --- Not for Publication 25 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Emerging Research Architectures ♦ Transfers proposed  Should we continue the “Homogeneous Multicore Section ♦ Other comments  Morphic Architectures might include: Associative Memory Processor; Cellular Nonlinear Networks; and Neuromorphic LSIs for collision avoid.  Should Emerging Memory Architectures be addressed in this Section?  Recommend evaluation of integrating energy sources, storage memory, low-power sensors, and computational engines  Consider using biological concepts for new architectures to obtain high energy efficiency.  Consider integration of biological elements

26. Work in Progress --- Not for Publication 26 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Critique Section for Memory &Logic Tech Entries ♦ Comments  Important section to survey technology trend of emerging research devices  Standard Deviation is very helpful  How and why were the Evaluation Criteria chosen?  Need much more discussion of the data.  How can we critically review Architectural approaches? Should we try?  Should we use different colors because our use of red, white and yellow has a different meaning than the use of these colors in other chapters of the ITRS.  We need to sure our Critique Section analysis is consistent with the text for the Technology Entries, e.g., we need to be sure the highs and lows in the Critique are addressed as strengths and research gaps in the text sections.

27. Work in Progress --- Not for Publication 27 ERD WG 12/06/08 & 12/14/08 Feedback on 2007 ERD Chapter Scope, Difficult Challenges, Taxonomy & Guiding Principles ♦ Scope: In general the Scope is very good. However, the statement “…, CMOS certainly will provide a platform processing technology for sometime beyond the end of dimensional scaling, exploiting the notion that the ultimately scaled MOSFET is a nearly ideal electronic charge-based device” is a rather strong statement. Is it too strong? Should we say something about the technology “cost” in the Scope? ♦ Difficult Challenges: The Difficult Challenges are very good. ♦ Guiding Principles  The five original Guiding Principles are very good.  The sixth Guiding Principle related to “Architecture” needs clarification as to whether it only applies to “Beyond CMOS” or to both “Beyond CMOS” and CMOS integrated with Beyond CMOS devices? That is do we address: (1) New architectures with conventional devices and/or (2) New architectures with beyond CMOS devices on CMOS infrastructure?.

28. Work in Progress --- Not for Publication 28 ERD WG 12/06/08 & 12/14/08 Decisions for 2009 Chapter ♦ Memory –Include device structural aspects of the new NW PCRAM in ERD with a summary of the materials issues. Include more materials information in ERM on this topic. –Include the Spin Torque Transfer MRAM in ERD/ERM. –Decide whether or not to include the “Magnetic Domain” or “Racetrack Memory” in ERD. We need to focus on  P applications. –We will keep nanomechanical memory in ERD Memory Table. –Move the Ferroelectric Effects Tunneling Barrier Memory from the Electronic Effects Memory category to the Memory Transition Table –Leave “Redox type” memories in the ERD. These are different than ionic cation migration effects memory. –By categorizing using a physics-based system, a given material that exhibits 2 or more effects will be listed in each category.

29. Work in Progress --- Not for Publication 29 ERD WG 12/06/08 & 12/14/08 Decisions for 2009 Chapter ♦ Logic –ERD/ERM recommends carbon-based nanoelectronics to include CNT, graphene for more resources and roadmapping for IRC as part of promising technologies for 5-10 years demonstration horizon –Carbon-based nanoelectronics will be included in the 2009 ERD chapter via a two new Potential Solutions tables – for materials and for device issues. –Seven potential technologies were considered: 1.Carbon-based Nanoelectronics 2.Collective spin 3.Spin torque transfer 4.Atomic and electrochemical metal 5.CMOL/FPNI 6.Single Electron Transistor 7.NEM S

30. Work in Progress --- Not for Publication 30 ERD WG 12/06/08 & 12/14/08 Comments 9/23/08 Does this include wires, vias, pkg technology, etc. – no For emphasis on Carbon-based NE Mike will connect w/ ESH Jim Jewett ERM Table of Applications & Proposed Structure –What is infrastructure mean? –Equipment issue is important. Potential Solution Chart –Don’t tie down the time frame too rigidly –Label chart by material or device structure –Label as More Moore and Beyond CMOS –Can we have a memory driver as we have a logic driver? –Entries

31. Work in Progress --- Not for Publication 31 ERD WG 12/06/08 & 12/14/08 Action Items (1/2) 1.Consider to include in the 2009 ERD Chapter the new chart entitled “Evolution of Extended CMOS” contributed by ERD Japan. BourianoffIn Process 2.Strengthen ties between US-EU-Asia. Requires good balance of representing members from three regions HutchbyIn Process 3.The best demonstrated parameters are obtained from different devices. Is it possible to obtain them simultaneously on one device? We should include a note to this effect. Bourianoff, Zhirnov 4.Extend the Mission of ERD to include additional Research Vectors proposed by the Japan ERD WG. These are Numbers 1 – 4 listed in Item No. 1 above. Bourianoff 5.Consider moving to PIDS in 2009: 1) III-V Alternate Channel Materials, and 2) Low Dimensional Materials. Discuss this with PIDS. (This discussion has begun.) BourianoffIn Process 6.Make the mission of ERD clear. Make it more Globally justified.Hutchby 7. Organize an ERD Working Group in KoreaIn U. ChungIn Process

32. Work in Progress --- Not for Publication 32 ERD WG 12/06/08 & 12/14/08 Action Items (2/2) 8.Bob Doering argued that the Critical Evaluation Chart gives the wrong message; a.We need to re-think this chart b.This chart assigns a different meaning to red than is used by all the other ITRS chapters. The other chapters use red to highlight a major research gap. c.We should point the directions into which “critical path” research should be directed. We need a way to distinguish a Fundamental Limit versus the Maturity of the Technology Entry Hutchby 9.Need a dialog with the Design and Systems Drivers ITWG to address synergy between the two chapters. Hutchby, Bourianoff, Yeh In Process 10.Discuss/decide upon expanding scope to include Sensors, Actuators, and Power Sources to encompass More than Moore or Functional Diversification Hutchby and Brillouet 11.Discuss other materials (in addition to NiO) for Fuse/Anti-fuse Memory Tech Zhirnov & Garner 12.Plan Memory FXF Meeting in Germany for April 2, 2008. Include Memory Expert Panel. ZhirnovDone 13.Write paper/proposal for NSF Funding for workshops.Hutchby/ZhirnovDone 14.Include Akinaga-san in Memory Working GroupZhirnovDone

33. Work in Progress --- Not for Publication 33 ERD WG 12/06/08 & 12/14/08 Critical Review on Critical Assessment 1. Changes in Critical Assessment (2007 2005) 2. Short Comments F. Nihey (NEC)

34. Work in Progress --- Not for Publication 34 ERD WG 12/06/08 & 12/14/08 ERD - Critical Assessment - Memory 2005 Edition 2007 Edition Molecular Polymer Insulator Resistance Change Ferroelectric FET Engineered Tunnel Barrier Nano Floating Gate Engineered Tunnel Barrier Fuse/Anti-Fuse Nano Mechanical Electron Injection Ionic Ferroelectric FET Macromolecular

35. Work in Progress --- Not for Publication 35 ERD WG 12/06/08 & 12/14/08 ERD – Critical Assessment - Logic 2005 Edition 2007 Edition Engineered Tunnel Barrier 1D Structure Channel Replacement Mat. Resonant Tunneling Single Electron Tunneling Molecular Ferromagnetic Spin Molecular Ferromagnetic Spin

36. Work in Progress --- Not for Publication 36 ERD WG 12/06/08 & 12/14/08 2005 2007 2005 2007 2005 2007 2005 2007 Evaluation - Memory

37. Work in Progress --- Not for Publication 37 ERD WG 12/06/08 & 12/14/08 2005 2007 2005 2007 2005 2007 Evaluation – Logic (1/2)

38. Work in Progress --- Not for Publication 38 ERD WG 12/06/08 & 12/14/08 Evaluation – Logic (2/2)

39. Work in Progress --- Not for Publication 39 ERD WG 12/06/08 & 12/14/08 Critical review: memory How can be improved? Something missing? Other comments? Suggestions: – for each memory candidate, include very short comments (arguments!) on the high-scored and low-scored features: main advantages versus open issues (when possible quantify comments). –when applicable, for each memory candidate, short comment about level of concrete demonstration and/or prospects for NV, SRAM, DRAM –identify contributors.

40. Work in Progress --- Not for Publication 40 ERD WG 12/06/08 & 12/14/08 Critical Review: overview Team: Jim Hutchby et al, Reviewer: Adrian M. Ionescu Goals:  assess each Technology Entry (TE) for Memory & Logic  compare/benchmark with/against: - Si CMOS logic - memory technology to displace  provide the ERD community with and funding agencies with ERD WG collective view of the overall (long term) potential of each TE

41. Work in Progress --- Not for Publication 41 ERD WG 12/06/08 & 12/14/08 ScalabilityPerformance Energy Efficiency Off/On ratio Operationa l Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility Engineered Tunnel Barrier Memory 2.42.32.22.02.22.7 2.5 Fuse/Anti-fuse Memory 2.61.92.02.21.82.82.72.5 Nano Mechanical Memory 1.71.92.42.51.92.92.2 Electron Injection Memory 2.32.22.32.12.02.42.32.4 321321 321321 321321 321321 Critical Review – Memory (1/2) > 20 >18 - 20 < 16 >16 - 18

42. Work in Progress --- Not for Publication 42 ERD WG 12/06/08 & 12/14/08 ScalabilityPerformance Energy Efficiency Off/On ratio Operational Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility Ionic Memory 2.62.02.42.11.72.52.12.5 Ferroelectric FET Memory 1.82.01.92.11.72.62.3 Macromolecular Memory 2.11.82.11.81.42.21.92.3 Molecular Memory 2.41.72.41.41.32.21.81.9 321321 321321 321321 321321 Critical Review – Memory (2/2) > 20 >18 - 20 < 16 >16 - 18