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1 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ITRS Public Conference Emerging Research Devices Makuhari, Japan December 5, 2007.

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Presentation on theme: "1 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ITRS Public Conference Emerging Research Devices Makuhari, Japan December 5, 2007."— Presentation transcript:

1 1 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ITRS Public Conference Emerging Research Devices Makuhari, Japan December 5, 2007 Jim Hutchby – SRC

2 2 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Hiroyuki AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoFujitsu George BourianoffIntel/SRC Michel BrillouetCEA/LETI Joe BrewerU. Florida John CarruthersPSU Ralph CavinSRC U-In ChungSamsung Philippe CoronelST Me Erik DeBenedictisSNL Simon Deleonibus LETI Kristin De MeyerIMEC Mike Forshaw UC London Michael FrankAMD Christian GamratCEA Mike GarnerIntel Dan HammerstromPSU Shigenori HayashiMatsushita Toshiro HiramotoU. Tokyo Dan HerrSRC Mutsuo HidakaISTEK Jim HutchbySRC Yasuo InoueRenesas Tech Adrian IonescuETH Kohei ItohKeio U. Seiichiro KawamuraSelete Rick KiehlU. Minn Tsu-Jae King LiuU. C. Berkeley Hiroshi KotakiSharp Nety KrishnaAMAT Zoran KrivokapicAMD Phil KuekesHP Lou LomeIDA Hiroshi MizutaU. Southampton Murali RamachandranFreescale Fumiyuki NiheyNEC Dmitri NikonovIntel Wei-Xin NiNDL Tak Ning IBM Kwok NgSRC Lothar RischInfineon Dave RobertsAir Products Kaushal SinghAMAT Kentaro Shibahara Hiroshima U. Sadas ShankarIntel Thomas Skotnicki ST Me Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Luan TranMicron Ken UchidaToshiba Yasuo WadaWaseda U. Rainer WaserRWTH A Frans Widdershoven NXP Jeff WelserNRI/IBM Philip WongStanford U. Kojiro YagamiSony David YehSRC/TI In-Seok YeoSamsung Makoto Yoshimi SOITEC In-K YooSAIT Peter ZeitzoffFreescale Yuegang ZhangIntel Victor ZhirnovSRC Emerging Research Devices Working Group

3 3 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Highlights of Changes Scope of ERD Chapter Invent the new switch – Emerging information processing* devices to eventually replace CMOS Boolean logic Supplement Si CMOS – Use the physics of emerging research devices to realize complex typically nonlinear functions in an accelerator-like fashion Perform certain functions more efficiently than digital CMOS Eventually extend CMOS and nanoelectronics to address new applications Spin off a new chapter on Emerging Research Materials Expand the Emerging Architecture Section Expand scope of the Emerging Logic Section – supplement CMOS Example: Image Processing using emerging research devices integrated on a CMOS Platform. Update the Emerging Memory Section * ERD Chapter includes the following elements of Information Processing: Data processing, storage and communication.

4 4 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 year Beyond CMOS Elements ERD-WG in Japan Existing technologies New technologies Evolution of Extended CMOS

5 5 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD Chapter Emerging Research Memory Devices

6 6 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD Chapter Transition Table for Emerging Memory Devices

7 7 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD Chapter Capacitance-based memory technologies Engineered tunnel barrier Memory Ferroelectric FET Memory Storage Mechanism Charge on floating gate Remnant polarization on a ferroelectric gate dielectric Cell Elements 1T Device Types Graded insulator FET with FE gate insulator

8 8 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD Chapter Resistance-based memory technologies

9 9 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ScalabilityPerformance Energy Efficiency Off/On ratio Operationa l Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility Engineered Tunnel Barrier Memory Fuse/Anti-fuse Memory Nano Mechanical Memory Electron Injection Memory Critical Evaluation Memory For each Technology Entry (e.g. 1D Structures), sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 > 20 > < 16 >

10 10 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ScalabilityPerformance Energy Efficiency Off/On ratio Operational Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility Ionic Memory Ferroelectric FET Memory Macromolecular Memory Molecular Memory Critical Evaluation Memory For each Technology Entry (e.g. 1D Structures), sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 > 20 > < 16 >

11 11 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD Emerging Research Logic Devices Device FET [B] 1D structures Resonant Tunneling Devices SET Molecular Ferromagnetic logic Spin transistor Types Si CMOS CNT FET NW FET NW hetero- structures Crossbar nanostructure RTD-FET RTT SET Crossbar latch Molecular transistor Molecular QCA Moving domain wall M: QCA Spin transistor Supported Architectures Conventional Conventional and Cross-bar Conventional and CNN CNN Cross-bar and QCA CNN Reconfigure logic and QCA Conventional Expand Transition

12 12 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Transition Table for Emerging Logic Devices

13 13 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD CMOS Scaling & Replacement Devices (1 st ) Device FETCMOS Extension Low dimensional structures CMOS Extension III-V channel replacement SETMolecularFerromagnetic logic Spin transistor Types Si CMOSCNT FET NW FET NW hetero- structures Nanoribbon transistors III-V compound semiconduct or channel replacement SET2-terminal 3-terminal FET 3-terminal bipolar transistor NEMS Molecular QCA Moving domain wall Hybrid Hall effect Magnetic Resistive Element M: QCA Spin Gain transistor HMF Spin MOSFET Spin Torque Transistor Supported Architectures Conventional Threshold logic Memory- based QCA Lithographically defined conventional

14 14 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ScalabilityPerformance Energy Efficiency Gain Operational Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility 1D Structure Channel Replacement Materials Single Electron Transistors Molecular Devices Critical Evaluation Logic For each Technology Entry (e.g. 1D Structures), sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 > 20 > < 16 >

15 15 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 ScalabilityPerformance Energy Efficiency Gain Operational Reliability Operate Temperature CMOS Technological Compatibility CMOS Architectural Compatibility Ferromagnetic Devices Spin Transistor Critical Evaluation Logic For each Technology Entry (e.g. 1D Structures), sum horizontally over the 8 Criteria Max Sum = 24 Min Sum = 8 > 20 > < 16 >

16 16 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Logic Device Conclusions Continued analysis of alternative technology entries likely will continue to yield the same result: Nothing beats MOSFETs overall for performing Boolean logic operations at comparable risk levels Certain functions, e.g. image recognition (associative processing), may be more efficiently done in networks of non-linear devices rather than Boolean logic gates

17 17 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Supplementing CMOS General Purpose Processor Basis of Existing Assessments of Logic Devices A possible ultimate evolution of on- chip architectures is Asynchronous Heterogeneous Multi-Core with Hierarchical Processors Organization Courtesy Fawzi Behmann - Freescale

18 18 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December ITRS ERD CMOS Supplement Devices (2 nd )

19 Emerging Research Architectures CMOL – Molecule on CMOS architecture CNN – Cellular Nonlinear Network AMP – Associative Memory Processor GPP – General Purpose Processor FG-MOS – Floating Gate MOS devices SET – single electron transistor ArchitectureImplementation Computational Elements NetworkApplication Research Activity Homogeneous Many-Core Symmetric coresCMOS Irregular/ Fixed Synthesis/GPP Heterogeneous Asymmetric cores CMOS Irregular/ Fixed Synthesis/GPP CMOL CMOS+Molecular Switches Irregular/ Fixed Synthesis/GPP Molecular Cross-bar Molecular Switches Regular/ Flexible Synthesis/GPP Check-point CMOS+ Ferromagnetic logic Irregular/ Fixed Synthesis/GPP Morphic CNNCMOS+Sensors Regular/ Flexible Recognition/Vision AMPFG-FET, SET Irregular/ Fixed Recognition/Vision Bio-inspired MFDT, Spin-gain transistor Mixed Recognition Mining Synthesis MFTD – multiferroic tunnel diode

20 20 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Image recognition Speech recognition DSP (cross correlation) Data Mining Optimization Physical simulation Sensory data processing (biological, physical) Image creation Cryptographic analysis Potential Supplemental Applications Illustrative Example

21 21 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Top down information processing Image Recognition Tadashi Shibata, University of Tokyo

22 22 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Specialized devices for image recognition Heterogate ferroelectric FGMOS FET Tadashi Shibata, University of Tokyo

23 23 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Image recognition Tadashi Shibata, University of Tokyo

24 24 ERD 2007 ITRS Winter Conference – Makuhari, Japan – 5 December 2007 Summary Scope: Broaden scope to encourage emerging technologies both to supplement CMOS as well as eventually to invent the new switch. Materials Section: Spin out a new cross-cut chapter on Emerging Research Materials. Memory Section: Added NEMS mechanical memory to section. –Divide Emerging Memory Tables into Resistive and Capacitive subcategories –Updated section in Logic Section: Reformulated Logic Device Section to encourage high potential, but high risk approaches while maintaining Technology Entry evaluation function. – Re-considered status of candidate Technology Entries. – Re-structured Logic Section. Architecture Section: Revised section to focus on encouraging research to explore optimal organization of emerging non-linear devices to efficiently realize accelerator-like functions to supplement the CMOS platform technology.


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