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1 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 ITRS Public Conference Emerging Research Devices 2012 ERD Chapter An Chen, Victor.

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Presentation on theme: "1 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 ITRS Public Conference Emerging Research Devices 2012 ERD Chapter An Chen, Victor."— Presentation transcript:

1 1 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 ITRS Public Conference Emerging Research Devices 2012 ERD Chapter An Chen, Victor Zhirnov and Jim Hutchby

2 2 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Hiro AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoKeio U. George BourianoffIntel Michel BrillouetCEA/LETI John CarruthersPSU Ralph CavinSRC Chorn-Ping ChangAMAT An ChenGLFOUNDRIES U-In ChungSamsung Byung Jin ChoKAIST Sung Woong ChungHynix Luigi ColomboTI Shamik DasMitre Antoine Khoueir Seagate Bob DoeringTI Tetsua EndohTohoku U. Bob FontanaIBM Paul FranzonNCSU Akira FujiwaraNTT Mike GarnerConsultant Dan HammerstromPSU Wilfried HaenschIBM Tsuyoshi HasegawaNIMS Shigenori HayashiMatsushita Dan HerrSRC Toshiro HiramotoU. Tokyo Matsuo HidakaISTEK Jim HutchbySRC Adrian IonescuEPFL Kiyoshi KawabataRenesas Tech Seiichiro KawamuraSelete Suhwan KimSeoul Nation U Hyoungjoon KimSamsung Atsuhiro KinoshitaToshiba Dae-Hong KoYonsei U. Hiroshi KotakiSharp Mark KryderINSIC Franz KreuplTech. U. Munich Zoran KrivokapicGLOBALFOUNDRIES Kee-Won KwonSeong Kyun Kwan U. Jong-Ho LeeHanyang U. Thomas LiewASTAR DSI Lou LomeIDA Matthew MarinellaSNL Hiroshi MizutaU. Southampton Kwok NgSRC Fumiyuki NiheiNEC Dmitri NikonovIntel Kei NodaKyoto U. Ferdinand PeperNICT Er-Xuan PingAMAT Yaw ObengNIST Yutaka OhnoNagoya U. Dave RobertsNantero Shintaro SatoFujitsu Labs Barry SchechtmanINSIC Sadas ShankarIntel Takahiro ShinadaWaseda U. Masayuki Shirane U. Tokyo Kaushal SinghAMAT Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Ken UchidaToshiba Thomas VogelsangRambus Yasuo WadaToyo U. Rainer WaserRWTH A Franz Widershoven NXP Jeff WelserNRI/IBM Philip WongStanford U. Dirk Wouters IMEC Kojiro YagamiSony David YehSRC/TI Hiroaki YodaToshiba In-K YooSAIT Victor ZhirnovSRC Emerging Research Devices Working Group

3 3 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 year Beyond CMOS Elements Existing technologies New technologies Evolution of Extended CMOS More Than Moore

4 4 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, ERD Chapter Assessing Emerging Research -- Memory Devices Logic Devices More-than-Moore Devices Architectures Benchmarking Emerging Devices

5 5 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Key Messages Emerging Research Memory: Remove Nanomechanical Memory from ERD technology table Recommend close tracking of RRAM by PIDS Workshops on Memory Select Devices and Storage Class Memory completed Quantitative data for roadmapping Implement multilevel energy analysis for different memory technologies Emerging Research Logic: Planned logic device workshop for maturity evaluation (Sep. 21) Recommend close tracking of p-III-V, n-Ge, nanowire FET, TFET by PIDS Add emerging interconnect discussions in ERD Together with RFAMS, mapping ERD devices for analog/RF applications More-than-Moore Section: New entry will be added in – On-chip energy harvesting devices Emerging Architectures: Execute workshop on emerging research architectures (fundamental concepts) Add emerging memory interface for Storage Class Memory

6 6 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Cross-TWIG Interactions Discussions with PIDS on emerging research memory and logic devices for close tracking of maturing technologies –RRAM –Nanowire FET, Tunnel FET, p-III-V, n-Ge Formed a taskforce with RF/AMS for evaluation of ERD devices for RF/Analog application –Envisioned outcome: a parametrization table in ERD MtM section Formed a taskforce with Interconnects for exploring emerging interconnects solutions for emerging research devices –Envisioned outcome: expanding ERD tables to include emerging interconnect solutions Initiated discussion with Design and AP on exploring circuit design and application space for ERD

7 7 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, ERD Workshops Workshop on assessment of options for emerging memory select devices –Noorwijk, the Netherlands, April 22, 2012 –Status: Completed and report finished Workshop on emerging architectures for storage class memory –Monterey, CA, July 8, 2012 –Status: Completed Workshop on emerging research logic devices –Bordeaux, France, September 21, 2012 (ESSDERC-linked) –Status: Agenda completed Workshop on emerging research architectures –San Francisco, CA, Dec 8, 2012 (tentative) –Status: TBD

8 8 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 One Diode – One Resistor (1D1R) Memory Cell H-S. P. Wong – Stanford U.

9 9 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, Select Device Workshop Outcome Workshop presentations will be put on ITRS website Workshop results are summarized in a report (finished) Several take-away messages –There are several categories of memory select devices depending on memory device type and applications e.g. RRAM or PCM; embedded vs. stand-alone ERD Storage Class Memory workshop in July 2012 reiterated the importance of select devices –A theoretical exploration of a selector-less memory cell needs to be performed Memory element with a build-in select element (e.g. a Schottky diode) Materials/structure optimization for both memory and select functions Materials and Devices modeling could provide an important insight –Contact resistance is an important practical performance limit ERM/ERD contact resistance e-workshop being planned

10 10 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Memory Hierarchy – Future Memory Challenge Source: Al Fazio (Intel) NVM cost/gigabyte ~ $1 SCM

11 11 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Storage-type vs. memory-type SCM ns 100ns 1 s 10 s 100 s Read Latency NAND DRAM (Write) Endurance Cost/bit Speed (Latency & Bandwidth) Power! Memory-type uses Storage-type uses low co$t Cell size [F 2 ] F F 4F 2 Source: G. Burr (IBM)

12 12 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, nm Pt TiO 2 TiO 2-x oxidized reduced ERD Memory Candidates

13 13 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Potential of Memory Candidates for SCM Applications 13 Prototypical (Table ERD3) Emerging (Table ERD5) ParameterFeRAMSTT-MRAMPCRAM Emerging ferroelectric memory Nanomechan ical memory Redox memory Mott Memory Macromolec ular memory Molecular Memory Scalability MLC 3D integration Fabrication cost Endurance ? ? ? ? ? ? ?

14 14 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Device options for SCM 14 Morning session

15 15 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Architecture issues of SCM 15 Afternoon session

16 16 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, SCM Workshop Outcome Over 50 participants Workshop presentations will be put on ITRS website Workshop results will be summarized in a report Several take-away messages –A comprehensive multilevel energy analysis of different memories is needed A follow-up ERD study is planned –Flexible interfaces (device-independent) A new topic for emerging architecture –'Generic' memory specs may need some discussion/rationalization –Some memory devices are unlikely candidates (e.g., FRAM, Macromolecular memory)

17 17 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 ERD Logic Workshop 17 9:00Overall workshop goals and objectivesGeorge Bourianoff / Intel - USA Session I: Circuit Requirements & Expectations for Emerging Research Devices 9:15Digital CircuitsDavid Frank / IBM - USA 9:45Analog/Mixed Signal/ RF CircuitsDavid Robertson / Analog Devices – USA 10:15More-than-Moore IdeasThomas Skotnicki / ST Microelectronics – France 10:45Break Session II: Emerging Research Devices for Nanocircuits 11:00Tunnel FETMarc Heyns / IMEC – Belgium 11:30CNT FETChongwu Zhou / USC – USA 12:00Graphene transistorsFrank Schwierz / TU Ilmenau – Germany (V.Z.) 12:30 – 14:00 Lunch 14:00NEMS DevicesAdrian Ionescu / EPF Lausanne – Switzerland 14:30Atomic switchTsuyoshi Hasegawa / NIMS – Japan 15:00MOTT FETAkihito Sawa / AIST – USA 15:30Break 15:45Spin FET and Spin MOSFETSatoshi Sugahara / Tokyo Inst Technol – Japan 16:15Nanomagetic and all spin logicMichael Niemier / U Notre Dame – USA 16:45Spin wave devicesAlexander Khitun / UCLA – USA 17:15Break 17:30Summary and wrap upGeorge Bourianoff / Intel – USA 18:00Adjourn

18 18 ERD 2012 ITRS Summer Conference – San Francisco, USA – July 12, 2012 Summary Emerging Research Memory: Remove Nanomechanical Memory from ERD technology table Recommend close tracking of RRAM by PIDS Workshops on Memory Select Devices and Storage Class Memory completed Quantitative data for roadmapping Implement multilevel energy analysis for different memory technologies Emerging Research Logic: Planned logic device workshop for maturity evaluation (Sep. 21) Recommend close tracking of p-III-V, n-Ge, nanowire FET, TFET by PIDS Add emerging interconnect discussions in ERD Together with RFAMS, mapping ERD devices for analog/RF applications More-than-Moore Section: New entry will be added in – On-chip energy harvesting devices Emerging Architectures: Execute workshop on emerging research architectures (fundamental concepts) Add emerging memory interface for Storage Class Memory


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