Presentation on theme: "1 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December, 2009 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC December 16,"— Presentation transcript:
1 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December, 2009 ITRS Public Conference Emerging Research Devices Jim Hutchby – SRC December 16, 2009 2009 ERD Chapter Emerging Memory Devices Emerging Logic Devices Emerging Architectures
2 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Hiroyugi AkinagaAIST Tetsuya AsaiHokkaido U. Yuji AwanoKeio U. George BourianoffIntel Michel BrillouetCEA/LETI Joe BrewerU. Florida John CarruthersPSU Ralph CavinSRC An ChenGLFOUNDRIES U-In ChungSamsung Byung Jin ChoKAIST Sung Woong ChungHynix Luigi ColomboTI Shamik DasMitre Erik DeBenedictisSNL Simon Deleonibus LETI Kristin De MeyerIMEC Bob FontanaIBM Paul FranzonNCSU Akira FujiwaraNTT Christian GamratCEA Mike GarnerIntel Dan HammerstromPSU Wilfried HaenschIBM Tsuyoshi HasegawaNIMS Shigenori HayashiMatsushita Dan HerrSRC Toshiro HiramotoU. Tokyo Matsuo HidakaISTEK Jim HutchbySRC Adrian IonescuETH Kohei ItohKeio U. Kiyoshi KawabataRenesas Tech Seiichiro KawamuraSelete Rick KiehlU. C. Davis Suhwan KimSeoul Nation U Hyoungjoon KimSamsung Tsu-Jae King LiuU.C. Berkeley Atsuhiro KinoshitaToshiba Dae-Hong KoYonsei U. Hiroshi KotakiSharp Franz KreuplQimonda Nety KrishnaAMAT Mark KryderINSIC Zoran KrivokapicGLOBALFOUNDRIES Phil KuekesHP Kee-Won KwonSeong Kyun Kwan U. Jong-Ho LeeKyungpook Nation U. Jong-Ho LeeHanyang U. Lou LomeIDA Hiroshi MizutaU. Southampton Kwok NgSRC Fumiyuki NiheiNEC Ferdinand PeperNICT Yaw ObengNIST Dave RobertsNantero Barry SchechtmanINSIC Kaushal SinghAMAT Sadas ShankarIntel Atsushi ShiotaJSR Micro Satoshi SugaharaTokyo Tech Shin-ichi TakagiU. Tokyo Ken UchidaToshiba Yasuo WadaToyo U. Rainer WaserRWTH A Franz Widdershoven NXP Jeff WelserNRI/IBM Philip WongStanford U. Kojiro YagamiSony David YehSRC/TI In-Seok YeoSamsung Hiroaki YodaToshiba In-K YooSAIT Yuegang ZhangLLLab Victor ZhirnovSRC Emerging Research Devices Working Group
3 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 year Beyond CMOS Elements Existing technologies New technologies Evolution of Extended CMOS More Than Moore ERD-WG in Japan
9 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 9 Content changes for Emerging Research Memory Section Recommend transfer of Engineered Tunnel Barrier Memory to PIDS and FEP Add Nano Wire Phase-Change Memory Add Spin Transfer Torque Magnetic RAM
11 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 New Logic Technology Tables Table 1 – MOSFETs Extending the Channel of MOSFETs to the End of the roadmap _____________ CNT FETs Graphene nanoribbons III-V Channel MOSFETs Ge Channel MOSFETs Nanowire FETs Non conventional geometry devices Table 2- Unconventional FETS, Charge-based Extended CMOS Devices _______________ Tunnel FET I-MOS Spin FET SET NEMS switch Negative Cg MOSFET Table 3 - Non-FET, Non Charge-based Beyond CMOS devices _______________ Collective Magnetic Devices Moving domain wall devices Atomic Switch Molecular Switch Pseudo-spintronic Devices Nanomagnetic (M:QCA)
2009 Logic Transition table TechnologyStatusReasonComment RTDoutNo viable logic functionality Has been tracked for multiple revisions Bi-layer tunneling devices InSignificant theoretical work in NRI Band to band tunneling devices In NEMSIn RSFQPossible future device
13 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Carbon-based Nanoelectronics Fullerenes (C 60 ) Carbon Nanotubes Graphite Graphene 0D1D2D3D Atomic orbital sp 2 P. Kim – Columbia U.
14 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Graphene Electronics: Conventional & Non-conventional Conventional Devices Cheianov et al. Science (07) Graphene Veselago lense FET Band gap engineered Graphene nanoribbons Nonconventional Devices Trauzettel et al. Nature Phys. (07) Graphene pseudospintronics Son et al. Nature (07) Graphene Spintronics Graphene quantum dot (Manchester group) P. Kim – Columbia U.
17 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Four Architectural Projections 1)Hdwre Accelerators execute selected functions faster than software performing it on the CPU. 2)Alternative switches often exhibit emergent, idiosyncratic behavior. We should exploit them. 3)CMOS is not going away anytime soon. 4)New switches may improve high utilitization accelerators
18 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Matching Logic Functions & New Switch Behaviors Single Spin Spin Domain Tunnel-FETs NEMS MQCA Molecular Bio-inspired CMOL Excitonics ? Popular Accelerators New Switch Ideas Encrypt / Decrypt Compr / Decompr Reg. Expression Scan Discrete COS Trnsfrm Bit Serial Operations H.264 Std Filtering DSP, A/D, D/A Viterbi Algorithms Image, Graphics Example: Cryptography Hardware Acceleration Operations required:Rotate, Byte Alignment, EXORs, Multiply, Table Lookup Circuits used in Accel: Transmission Gates (T-Gates) New Switch Opportunity: A number of new switches (i.e. T-FETs) dont have thermionic barriers: wont suffer from CMOS Pass-gate V T drop, Body Effect, or Source-Follower delay. Potential Opportunity: Replace 4 T-Gate MOSFETs with 1 low power switch.
20 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Improving Memory Power Efficiency Critical Needs -- Reduced power SRAM replacements 45 nm L1 Cache: 3.6 pJ/bit Note: re-architecting in 3D potentially can save ~50% What is the potential for an ERD to reduce to 0.3 pJ/bit? Reduced power switched interconnect Esp. packet routed interconnect (NOC) What is the potential for a memory-style ERD to be used for fast switchable interconnect?
21 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 For both General Purpose and Application Specific Computing, the bottleneck is not in logic operations but in memory, communications, and reliability 3DIC creates new opportunity for algorithms and architectures that benefit from locality ERD could benefit from a 1R1D cell –1 Resistor 1 Diode (1R1D) potentially as useful as 1 Resistor 1 Transistor (1R1T) –Gives better scaling Memory Architecture Preliminary Observations
23 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 2/6/2014 23 Architecture by Inference Intelligent Computing Large class of problems that computers still do not solve well Lack of general solutions to these problems constitutes a significant barrier to computer usage and huge potential markets Traditional Rule Based Knowledge systems are now evolving into probabilistic structures where inference becomes the key computation, generally based on Bayes rule
Maseeh College of Engineering and Computer Science Hammerstrom 2/6/2014 24 Bayesian Networks We now have Bayesian networks Bayesian nets express the structured, graphical representations of probabilistic relationships between several random variables And the fundamental computation has become probabilistic inference P(d|b,c)d1d1 d2d2 b 1, c 1 0.5 b 2, c 1 0.30.7 b 1, c 2 0.90.1 b 2, c 2 0.80.2
25 ERD 2009 ITRS Winter Conference – Hsinchu, Taiwan – 16 December 2009 Process for Technology Transfer to PIDS/FEP made explicit Logic Devices New Logic Table structure defined to identify three device categories (1 – Extend CMOS; 2 – Charge-based Non-CMOS; 3 – Non-charge- based Beyond-CMOS) New potential solution table for Carbon-based Nanoelectronics Memory Devices Transfer Engineered Tunnel Barrier Memory to PIDS/FEP A new taxonomy for categorizing resistive memories introduced. STT RAM and Nano-wire PCM scaled beyond 15nm STT RAM included in ERD to complement entry in PIDS/FEP An assessment of new memory devices is underway. Architecture New Architectural work for benchmarking Beyond CMOS devices New Architecture section includes 1) memory architecture, 2) a new inference compute proposal, and 3) a conceptual thermodynamic method for evaluating architecture. ERD – Key Messages
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