1. Work in Progress --- Not for Publication 1 PIDS 7/11/00 PIDS ITWG Meeting PIDS ITWG Emerging Research Devices Working Group Face-to-Face Meeting Jim Hutchby - Facilitating Room: Mont Blanc 2 Atria Novotel - Grenoble, France 8:00 a.m - 4:00 p.m. April 25, 2001

2. Work in Progress --- Not for Publication 2 PIDS 7/11/00 PIDS ITWG Novel Devices Working Group Participants u George BourinaoffIntel/SRC u Joop BruinesPhilips u Joe BrewerU. Florida u Jim ChungCompaq u Peng FangAMAT u Steve HilleniusAgere u Toshiro HiramotoTokyo U. u Jim HutchbySRC u Dae Gwan KangHyundai u Makoto Yoshimi Toshiba u Kentarou Shibahara Hiroshima U. u Kristin De MeyerIMEC u Tak Ning IBM u Byong Gook ParkSeoul N. U. u Luan TranMicron u Bin ZhaoConexant u Victor ZhirnovSRC/NCSU u Ramon CompanoEurope Com

3. Work in Progress --- Not for Publication 3 PIDS 7/11/00 PIDS ITWG Emerging Devices Working Group Working Group Objectives Prepare a sub-section of the 2001PIDS ITRS uAssess advanced non-bulk CMOS-related technologies uAssess potential and issues related to novel devices and technologies related to: v Logic v Memory v Information Processing Architectures

4. Work in Progress --- Not for Publication 4 PIDS 7/11/00 PIDS ITWG Emerging Devices Working Group Meeting Objectives & Desired Outcomes u Complete the Emerging Research Devices Tables – Non Bulk CMOS – Research Memory Devices – Logic Devices – Technologies – Architectures u Complete design and layout of the Emerging Technology Sequence Chart u Set Working Group Agenda for completing our section – Emerging Technology Sequence Chart (July ITRS Mtg.) – Text descriptions of Table Entries (July ITRS Mtg.) – Reference text for Table Entries (July ITRS Mtg.) – Completed Emerging Research Devices Section (8/30)

5. Work in Progress --- Not for Publication 5 PIDS 7/11/00 PIDS ITWG Emerging Devices Working Group Agenda 8:00Introductions 8:15Review meeting objectives and agenda Hutchby 8:30Review status of Emerging Research Hutchby Devices Section u Tables (technology entries & row metrics) – Identify points of consensus – Identify issues not having consensus u Emerging Technology Sequence Chart 9:00 Discuss Tables 9:00Non-Bulk CMOS Table Yoshima 9:45Memory Table Zhirnov 10:00Break 10:15Memory Table (continued) Zhirnov 11:00Logic Table Compano 12:00Lunch 1:00Technology Table Hutchby 2:00Architecture Table Bourianoff 3:00Emerging Technology Sequence Chart Hutchby 4:00 Adjourn Meeting

6. Model Table for Non-Bulk CMOS Devices PIDS ITWG Emerging Research Devices Working Group

7. Work in Progress --- Not for Publication 7 PIDS 7/11/00

8. Work in Progress --- Not for Publication 8 PIDS 7/11/00 Emerging Research Logic Devices 1 PIDS ITWG Emerging earch Devices Working Group 1 The time horizon for entries increases from left to right in these tables

9. Work in Progress --- Not for Publication 9 PIDS 7/11/00 Model Table for Emerging Technologies 1 PIDS ITWG Novel Devices Working Group 1 The time horizon for entries increases from left to right in these tables

10. Work in Progress --- Not for Publication 10 PIDS 7/11/00 Emerging Research Architectures PIDS ITWG Emerging Research Devices Working Group

11. Work in Progress --- Not for Publication 11 PIDS 7/11/00 Feature Size: Technology Progression Bulk CMOS PD SOI CMOS Double-Gate CMOS High mobility (strained Si on SiGe) High k gate dielectric Molecular devices Self-assembly Metal gate Nanotube Wafer bonding & layer transfer 3D, heterogeneous integration 100 nm15 nm Time 2 nm Nanometer- scale CMP Air bridge Cu interconnect Low-k ILD Technology features (add-ons) Molecular devices Nanotechnology Contacts to nanodevices Interconnects for nanodevices

12. Work in Progress --- Not for Publication 12 PIDS 7/11/00 Critical Size Emerging Technology Sequence 1 1 This chart is intended to guide research. It is not intended to predict future technologies Bulk CMOS PD SOI CMOS Double-Gate CMOS High mobility (strained Si / SiGe) High k gate dielectric Molecular devices Self-assembly Metal gate Nanotube Wafer bonding & layer transfer 3D-integration 100 nm15nm Nanometer- scale CMP Air bridge Cu interconnect Low-k ILD Contacts to nanodevices Interconnects for nanodevices 20052020Year 2nm50nm 2010 CNN & QCA networks Devices Architecture Technology

13. Work in Progress --- Not for Publication 13 PIDS 7/11/00 NDWG Issues Non Bulk CMOS Devices uShould we have an entry for Fully Depleted SOI or just a single entry for SOI without specifying PD or FD. We are all agreed that we should have some kind of entry for SOI. The question is whether the entry should refer to SOI or to FD-SOI? uDouble gate structures. The Japan Region proposes to discuss 1) Vertical MOSFET, 2) DELTA, 3) double-gate MOSFET separately.

14. Work in Progress --- Not for Publication 14 PIDS 7/11/00 NDWG Issues Emerging Logic Devices uNovel Logic Devices. Should we refer to this table as the Emerging Logic Devices Table? Other tables could be similarly named, e.g., Emerging Memory Devices Table, etc. uWhat position should we take regarding application of the NDWGs judgement on the various entries? Should we leave any out if we think they are too speculative? uAdded Row Metric. The US Group added a new row metric entitled Maturity. This metric is proposed to be added to all the tables

15. Work in Progress --- Not for Publication 15 PIDS 7/11/00 NDWG Issues Emerging Logic Devices uGiven our position on the RTD and its lack of potential, due to its being a 2-terminal device, what position should we take on the newer versions of 2-terminal devices, such as molecular switches, consisting of single molecules operating in a tunneling mode? We all agree that we should have an entry for single molecular devices and for Carbon Nanotubes. Also, the Far East Region view is that we should keep the sub-category for RTD 2-terminal devices. The US Region agrees that we should keep the entry for the RTD 2-terminal device in the RTD-FET section.

16. Work in Progress --- Not for Publication 16 PIDS 7/11/00 NDWG Issues Emerging Memory Devices uMRAM. Should we separate the entries for GMR and Tunnel Junction Devices? uMRAM. The title Pseudo-Spin-Valve Memory might be substituted for GMR Memory.

17. Work in Progress --- Not for Publication 17 PIDS 7/11/00 NDWG Issues Emerging Memory Devices uWe need more discussion of how best to group these different memory types, and how best to categorize them with descriptive titles. Cell size, access time, retention time, write cycles and power. uShould the Yano Device be a separate entry to the Memory Table? uCrested Tunnel Barrier Memory. A concern is this title is specific to Prof. Liharevs approach. Several other names including Nano Floating Gate have been suggested. uCoulomb Blockade Memory. Concern has been expressed that this title is not descriptive. Another title of Single Electron Memory has been suggested.

18. Work in Progress --- Not for Publication 18 PIDS 7/11/00 NDWG Issues Emerging Architectures uWe need to decide whether and where to put 3-D Heterogeneous Integration? Specifically, do we put the 3-D Heterogeneous Integration in the Emerging Architecture Table? The US Region agrees this should be in the Emerging Architectures Table. uWe need to decide whether or not to keep the entries for Defect Tolerant Architecture and Molecular Computing in the Emerging Architecture Table?