1. PHOTOLITHOGRAPHY STUDY FOR HIGH-DENSITY INTEGRATION TECHNOLOGIES
Hiromi Suda
Canon Inc.
October 14th, 2015

2. Outline 1. Introduction of 3D/2.5D technology
2. Lithography tool for 3D/2.5D integration
3. Challenges related to FOWLP
4. Summary

3. Outline 1. Introduction of 3D/2.5D technology
2. Lithography tool for 3D/2.5D integration
3. Challenges related to FOWLP
4. Summary

4. Intro of 3D/2.5D technology
3D/2.5D integration technology is an innovative approach to high-density integration
3D (by TSV)
2.5D (by Si Interposer)
Memory
Si Interposer
Memory
Processor
Under the present conditions
3D/2.5D integration cost is still very high
3D/2.5D adoption is limited to high performance products

5. FOWLP technology
In FOWLP, semiconductor chips are connected using RDL, but without the use of a Si interposer
FOWLP overcomes pin count limitations by expanding RDL patterns to larger than the size of the chip
Mold
Processer
Memory

6. Outline 1. Introduction of 3D/2.5D technology
2. Lithography tool for 3D/2.5D integration
3. Challenges related to FOWLP
4. Summary

7. LITHOGRAPHY TOOL COMPATIBLE WITH 3D/2.5D
Equipped with functions for Advanced Packaging
Through Si Alignment
Alignment
Unique Pattern TVPA
Dual Side Metrology
Exposure
Optimal NA lens
Wide Band i-Line Filter
Special Items
Wafer Edge Shielding
Chemical Filter
Outgas Exhaust Unit
Pellicle Particle Checker
Wafer Edge Exposure
Chuck for warped wafer
Bonded wafer handling
Wafer

8. LITHOGRAPHY TOOL COMPATIBLE WITH 3D/2.5D
Equipped with functions for Advanced Packaging
Through Si Alignment
Alignment
Unique Pattern TVPA
Dual Side Metrology
Exposure
Optimal NA lens
Wide Band i-Line Filter
Special Items
Wafer Edge Shielding
Chemical Filter
Outgas Exhaust Unit
Pellicle Particle Checker
Wafer Edge Exposure
Chuck for warped wafer
Bonded wafer handling
Wafer

9. Hole pattern profiles for TSV
Focus
-6 µm
-4 µm
-2 µm
0 µm
2 µm
4 µm
6 µm
FPA-5510iV (NA0.18), 1.5 µm Hole
FPA-5510iZ (NA0.57), 2.5 µm Hole
Resist: P-W1000T-PM
Tokyo Ohka Kogyo (TOK), t = 5.5 µm

10. DOF for 1 μm pattern FPA-5510iV achieves large common DOF
Reduction optics
New chuck system
Die-by-die tilt & focus
FPA-5510iV
Target 1.0 μm L/S
Image Field 52 ×34 mm
Measurement points: 9 points
12.2μm
Focus (μm)
ΔCD (%)
Measurement points
52 mm
34 mm

11. LITHOGRAPHY TOOL COMPATIBLE WITH 3D/2.5D
Equipped with functions for Advanced Packaging
Through Si Alignment
Alignment
Unique Pattern TVPA
Dual Side Metrology
Exposure
Optimal NA lens
Wide Band i-Line Filter
Special Items
Wafer Edge Shielding
Chemical Filter
Outgas Exhaust Unit
Pellicle Particle Checker
Wafer Edge Exposure
Chuck for warped wafer
Bonded wafer handling
Wafer

12. 3D-Alignment Scope Through Si Alignment Scope “TSA-Scope” with IR
Both front and back-side alignment is possible
Suitable for via-last processes
Transmittance of Si wafer (%)
Wavelength (nm)
FEOL
Through Si detection
with IR-light
Observed
Alignment mark
Through Si
Front surface detection with visible-light
Si-wafer

13. Overlay accuracy Overlay accuracy with FEOL machine
Si Wafer thickness: 775 µm
Back side (1st) patterning: FPA-5510iZ
Front side (2nd) patterning: FPA-5510iV
112nm
95nm
TSA-Scope overlay accuracy is <120 nm
TSA-Scope is suitable for TSV processes

14. LITHOGRAPHY TOOL COMPATIBLE WITH 3D/2.5D
Equipped with functions for Advanced Packaging
Through Si Alignment
Alignment
Unique Pattern TVPA
Dual Side Metrology
Exposure
Optimal NA lens
Wide Band i-Line Filter
Special Items
Wafer Edge Shielding
Chemical Filter
Outgas Exhaust Unit
Pellicle Particle Checker
Wafer Edge Exposure
Chuck for warped wafer
Bonded wafer handling
Wafer

15. Wafer Edge Application
Wafer Edge Shield
Wafer Edge Exposure
Edge Blade θ R
Exposure Area
No throughput loss
Variable exposure
width & position
Flexible ring-shaped shield
No contamination

16. Evaluation of wafer edge processing
Wafer Edge Shield
Wafer Edge Exposure
(mm)
Resist type : positive
Bump pattern
(µm)
Wafer Edge Shield & Exposure unit can make a smooth ring area around the wafer edge regardless of the shot layout

17. Outline 1. Introduction of 3D/2.5D technology
2. Lithography tool for 3D/2.5D integration
3. Challenges related to FOWLP
4. Summary

18. Key challenges of FOWLP
Large topography
Issue related to fine pitch RDL patterning
Die grid error
Issue related to high-density interconnections
Rotation A B
Magnification A B
Shift A B A B
Shot area
Bonded chip A
Bonding accuracy
chip to chip B
Non-flatness A B B A B A

19. Topography of FOWLP-Wafer
Sample wafer provided by Hitachi Chemical
Chip Size: 10 mm x10 mm;
Step size: 30 mm x 30 mm A A’
A-A’ Cross Section
Chip
20 μm
Mold
Focus gap between chips and mold region is ~20 μm
Focus gap reduces focus margin for fine RDL patterning

20. Die-by-Die tilt & focus
Shot size : 30 mm×30 mm
Original topography
Focus compensation residual
10 μm
20 μm
Multi-channel optical Auto-Focus system is available to support RDL patterning processes
Performs tilt & focus measurement on every shot
Reduces yield loss caused by the focus gap between die and mold

21. Resolution for FOWLP-Wafer
DOF Condition
CD Error:±5%
Dose Error: 7%
Focus compensation residual
Global focus
Die-by-die
tilt & focus
We expect that the required resolution will be 1um
in the future 3D/2.5D stacking processes.
DOF for isolated pattern with different NAs
is simulated in this graph.
The graph shows DOF of FPA-5510iV stepper at NA of 0.18.
It also shows the result of FPA-5510iZ front-end stepper at NA of 0.57.
The horizontal axis shows the width of an isolated pattern.
The vertical axis shows DOF.
NA of 0.18 provides sufficient DOF of 7um at the 1um line width.
2μm pattern can be formed with Die-by-die tilt & focus
Wafer flatness needs to be lower < 5μm for 1μm patterning

22. Die grid error of FOWLP-Wafer
Sample wafer consists of multi-chips package which two dies; die A and die B A B
Shot size
17mm x17mm

23. Die grid error of FOWLP-Wafer
Die grid measurement result on 3 sample wafers which manufactured in the same lot
Die A Placement Error
Die A
Wafer
3σ X (μm)
3σ Y (μm)
ID1
5.7
13.2
ID2
14.0
10.2
ID3
9.6
11.3
ID1 ID2 ID3
Die B Placement Error
Die B
Wafer
3σ X (μm)
3σ Y (μm)
ID1
6.4
16.0
ID2
14.6
12.1
ID3
11.3
12.2
Die grid error will be more crucial for fine pitch RDL

24. Compensation simulation by Global Alignment
We simulated how much Die A overlay error occurred after Global Alignment for Die A
Die A Overlay Error
Wafer
3σ X (μm)
3σ Y (μm)
ID1
5.7
13.2
ID2
14.0
10.2
ID3
9.6
11.3
ID1 ID2 ID3
Remove X,Y-mag. X,Y-rot.
Wafer
3σ X (μm)
3σ Y (μm)
ID1
4.2
7.4
ID2
4.9
8.6
ID3
4.5
Global overlay error compensation is not enough… 　　
Grid error has many non-linear components

25. Compensation simulation by Die-by-Die Alignment
Die-by-die Alignment for Die A can dramatically reduce overlay error for Die A
How much overlay error is there for Die B?
Die A
Compensated ideally in each shot
ID1 ID2 ID3
Die B Overlay Error
Die B
Wafer
3σ X (μm)
3σ Y (μm)
ID1
3.9
9.1
ID2
6.3
7.5
ID3
7.1
6.5
Relative position accuracy of dies in each shot is a key challenge

26. Overlay error summary
The stepper has an advantage for FOWLP because of wafer grid compensation
for molding & chip mounting error
Original
Global
Alignment
for die A
Die-by-die
Alignment
for die A
Die A
Die B
Die A
Die B
Die A
Die B

27. Alignment tree study
Wafer topography in FOWLP is increased after RDL and PBO layers are layered up
RDL
patterning position
Alignment mark
patterning position
Defocus
Die
Molding compound
Scribe Line
Alignment mark patterns are deteriorated due to defocus

28. Comparison of alignment marks
New alignment mark is robust for defocus
Enables us to use sequential alignment tree using cutting line alignment marks
Focus
　 μm μm　　 μm
40 μm
4 μm
Deteriorating
29 μm
General Mark
Suggested Mark
30 μm
30 μm
15 μm
Hole
Stable image

29. Outline 1. Introduction of 3D/2.5D technology
2. Lithography tool for 3D/2.5D integration
3. Challenges related to FOWLP
4. Summary

30. Summary
FOWLP technology may be an attractive alternative to 3D & 2.5D technology due to cost reductions
FPA-5510iV functions work well to support 　high- yield 3D/2.5D integration and FOWLP technology
Canon will contribute even more toward diversifying high-density integration technology

31. Canon will contribute to the success of high-density integration technology. Thank you for your attention Hiromi Suda Canon Inc.
Thank you for your attention.

33. LITHOGRAPHY TOOL COMPATIBLE WITH 3D/2.5D
Vertical thick resist patterning
Large DOF lens: NA0.18
Enables thick resist patterning with good profile
3D alignment capability
Through Silicon Alignment Scope (TSA-Scope)
Enables backside mark detection
Wafer edge processing
Wafer Edge Shield (WES)
Wafer Edge Exposure (WEE)
Enables ~20% higher chip yield

34. FPA-5510iV Basic performance
Item
Specification
Projection Lens
Magnification
2:1 NA
0.18
Field Size
52 x 34 mm
Resolution
≤ 1.50 μm
Illumination
Wavelength
365 nm
Intensity
≥ 13,000 W/m2
Overlay Accuracy
≤ 0.15 μm

35. Isolated pattern DOF
NA0.18 provides sufficient DOF & resolution for 3D/2.5D applications
DOF Condition
CD Error: ±5%
Dose Error: 7%

36. Wafer edge applications for plating processes
Resist must be removed from the wafer edge for electrolytic plating
Non-patterned Area
Seal Rubber
Plating Solution
Plating
Contact
Resist Removed Area
Resist
Wafer
Resist Hole
Expose
Shield
Positive Resist
Shield
Expose
Negative Resist

37. Wafer Edge Shield function “WES”
Flexible ring-shaped shield around the wafer edge
No contamination
Projection Lens
Illuminator
Wafer Edge Shield (WES) unit
Edge Blade θ R
Exposure Area

38. Wafer Edge Exposure “WEE”
No throughput loss
High intensity
Exposure at pre-alignment station during exposure of preceding wafer
Variable exposure width & position
Ring shape exposure available; Outside and inside edge can be set independently
WEE
Variable width
Variable position
Exposure Area

39. Advantage of “ring-shaped” area for plating
Chip Size: 7 mm×7 mm; Shot size: 49 mm×28 mm
Ring-shaped area: 3 mm from wafer edge
Non Ring-Shaped
Ring-Shaped
1092 chips
1292 chips
Ring-shaped
Non-patterned
Area
Nearly 20% yield improvement