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Numerical Technologies, Inc 4-13-99 Tutorial on Subwavelength Lithography DAC 99 Y. C. (Buno) Pati Numerical Technologies, Inc.

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Presentation on theme: "Numerical Technologies, Inc 4-13-99 Tutorial on Subwavelength Lithography DAC 99 Y. C. (Buno) Pati Numerical Technologies, Inc."— Presentation transcript:

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2 Numerical Technologies, Inc Tutorial on Subwavelength Lithography DAC 99 Y. C. (Buno) Pati Numerical Technologies, Inc.

3 DAC 99 June 24, 1999 Agenda Background The SubWavelength Gap SubWavelength Technologies  Optical proximity correction (OPC)  Phase shifting  Process modeling  Silicon Level Verification Some implications for physical design?

4 DAC 99 June 24, 1999 Optical Lithography Image of circuit patterns projected onto wafer Feature size limited by diffraction effects Rayleigh limits Resolution Depth of focus  Mask Silicon Wafer Illumination (Wavelength ) Numerical Aperture:

5 DAC 99 June 24, 1999 Mask Types Bright Field Masks  Opaque features defined by chrome  Background is transparent  Used e.g. for poly, metal,... Dark Field Masks  Transparent features defined  Background is opaque (chrome)  Used e.g. for contacts,... Clear areas Opaque (chrome) areas

6 DAC 99 June 24, 1999 Next Generation Lithography Technologies Extended UV EUV - 13nm wavelength x-rays Electron beams Common characteristics:  At least 10 years away  Requires significant research and development  Requires major infrastructure changes  More than 25 years of infrastructure and experience supporting supporting optical lithography

7 DAC 99 June 24, 1999 The SubWavelength™ Gap Lithography Wavelength Silicon Feature Size

8 DAC 99 June 24, 1999 The Impact of SubWavelength Lithography Traditional (WSYIWYG) relationship between layout, mask and silicon is no longer valid due to process distortions, OPC, and phase shifting LAYOUT MASK SILICON WAFER

9 DAC 99 June 24, 1999 Bridging the SubWavelength™ Gap

10 DAC 99 June 24, 1999 Optical Proximity Correction (OPC) Original Layout 0.18  m Conventional (no OPC) OPC Layout Silicon Image w/o OPC Silicon Image with OPC Corrective modifications to improve process control  improve yield  improve device performance

11 DAC 99 June 24, 1999 Phase-Shifting (PSM) Technology Original Layout 0.18  m Silicon Image with PSM Silicon Image w/o PSM Gate lengths reduced to 0.1  m PSM Layout Phase modulation used at mask level to  reduce feature size  improve yield  improve device performance

12 DAC 99 June 24, o phase shifter With Phase Shifting Opaque Without Phase Shifting Mask Light Source Transparent Wafer 0.11  m 0.11  m silicon features printed using a 0.35  m nominal process Scanning Electron Micrograph (SEM) courtesy Hewlett Packard Insufficient image contrast to successfully print silicon features

13 DAC 99 June 24, micron transistors fabricated with the same 0.18 micron process and NTI phase shifting technology SEM Courtesy Motorola 0.18 micron transistors fabricated with a 0.18 micron process 0.18  m 0.09  m

14 DAC 99 June 24, 1999 Optical Proximity Correction Goal: Improve device performance and yield  Cosmetic correction complicates mask manufacturing and dramatically increases cost with little benefit OPC is not new, it’s just more complicated than it was before Key issues:  Manufacturability  Design and verification tools OPC Features  Serifs - for corner rounding  Hammerheads - for line-end shortening  Assists - for CD control  Biasing - for CD control

15 DAC 99 June 24, 1999 Approaches to OPC Rule-Based OPC Apply corrections based on a set of pre- determined rules Fast design time Lower mask complexity Suitable for less “aggressive” designs Model-Based OPC Use process simulation to determine corrections on-line Longer design time Increased mask complexity Suitable for “aggressive” designs

16 DAC 99 June 24, 1999 Phase-Shifting - Background Proposed for lithography application in 1982 by Marc Levenson (IBM) Heightened interest in early 90’s  Near wavelength - no pressing need  Infrastructure, i.e. design automation, mask manufacturing,... not in place Many different forms of phase-shifting proposed Key issues:  Manufacturability  Design and verification tools

17 DAC 99 June 24, 1999 Some Forms of Phase-Shifting Masks Bright Field Phase-Shifting  Single exposure  Phase transitions required e.g. 60, 120, 90, 270  Throughput unaffected  Limited improvement in process latitude  Mask manufacturing difficult  Double exposure  PSM with 0 and 180 degree phase shifters + binary trim mask  Excellent process latitude  Decrease in throughput  270     00

18 DAC 99 June 24, 1999 Poly Active Phase Shifters Dark Field PSM Prints 0.11  m lines Original Design Binary Mask (0.20  m) Prints 0.20  m line Prints 0.11  m gates ++ Gate Shrinking and CD Control Using Phase Shifting

19 DAC 99 June 24, 1999 DUV, NA=0.60,  0.50 Chrome Mask Combined PSM Image Formation Using Double Exposure Phase Shifting

20 DAC 99 June 24, 1999 Phase Shifting Improves Critical Dimension (CD) Control PSM (150 nm L/ 300 nm S)BIM (250 nm L/S ) Line width contours shown for a full wafer (45 fields, 36 measurements per field. Contour interval: 5nm. DUV, NA = 0.42,  = 0.5 (Joint work with Hua-Yu Liu*, HP ULSI Research Laboratories) * Now at Numerical Technologies

21 DAC 99 June 24, 1999 Wafer Dimension (  m) Mask Dimension (  m) X 180° 0° Phase Shifting Binary DUV, NA=0.57,  =0.40 Controlling Silicon Dimensions Phase Shift vs. Binary

22 DAC 99 June 24, 1999 SubWavelength Infrastructure Physical Design Extraction Verification Mask Manufacturing Defect Inspection Repair EDA Software Tools Process Optimization Design Rule Generation Process Simulation and Development Tools Inspection and Repair Equipment SubWavelength Design Tools SubWavelength Inspection/Repair SubWavelength Process Development Mask FAB Design Subwavelength Production Process

23 DAC 99 June 24, 1999 Phase-shifting Technology Impacts Physical Layout Phase conflicts occur when two objects with minimum spacing cannot be assigned contrasting phase Layout designers must ensure that layouts are free of phase conflicts This is analogous to, but not the same as checking design rules 180 ° 0°0° 0°0° Phase Conflict Conflict Eliminated

24 DAC 99 June 24, 1999 SubWavelength Design and Manufacturing Data Flow

25 DAC 99 June 24, 1999 layout stepper optics etch photo resist Lithography Process printed pattern simulated printed pattern Process Model calibrated model Calibrated Process Simulation Models mask process

26 DAC 99 June 24, 1999 Calibrated Process Model InputsOutputs Process Measurements Process Simulation Applications of Process Models OPCPhase Shifting PS & OPC Rule Generation Mask InspectionSilicon DRCSi Image Extraction Process Model Calibrator

27 DAC 99 June 24, 1999

28 DAC 99 June 24, 1999 Design Silicon - DRC X Silicon - LVS X Silicon - Timing X Silicon Level Verification PASS ! Layout - DRC Layout - LVS Layout - Timing Physical Verification Layout Compares silicon to layout Silicon level verification can catch silicon failures prior to commiting to masks and silicon FAIL! Silicon Verification - Silicon vs. Layout

29 DAC 99 June 24, 1999 Silicon image simulation checks against target, and flags failures How does it work?

30 DAC 99 June 24, 1999 Summary SubWavelength technologies are critical to IC manufacturing for the next 7-10 years  OPC is a corrective technology  Phase shifting is an enabling technology SubWavelength design and manufacturing requires the coordinated interaction of physical design with lithography process, semiconductor equipment, and mask manufacturing Moore’s Law will live on (for now)! …. ….


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