1. VLSI Design Lecture 5: Logic Gates Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Wayne Wolf’s lecture notes

2. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Topics n Combinational logic functions. n Static complementary logic gate structures.

3. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Combinational logic expressions n Combinational logic: function value is a combination of function arguments. n A logic gate implements a particular logic function. n Both specification (logic equations) and implementation (logic gate networks) are written in Boolean logic.

4. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Gate design Why designing gates for logic functions is non-trivial: –may not have logic gates in the libray for all logic expressions; –a logic expression may map into gates that consume a lot of area, delay, or power.

5. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Boolean algebra terminology n Function: f = a’b + ab’ n a is a variable; a and a’ are literals. n ab’ is a term. n A function is irredundant if no literal can be removed without changing its truth value.

6. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Completeness n A set of functions f1, f2,... is complete iff every Boolean function can be generated by a combination of the functions. n NAND is a complete set; NOR is a complete set; {AND, OR} is not complete. n Transmission gates are not complete. n If your set of logic gates is not complete, you can’t design arbitrary logic.

7. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Static complementary gates n Complementary: have complementary pullup (p-type) and pulldown (n-type) networks. n Static: do not rely on stored charge. n Simple, effective, reliable; hence ubiquitous.

8. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Static complementary gate structure Pullup and pulldown networks: pullup network pulldown network V DD V SS out inputs

9. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter a out +

10. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter layout (tubs not shown) a out + transistors GND VDD aout tub ties

11. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NAND gate + b a out

12. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NAND layout + b a out b a VDD GND tub ties

13. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NOR gate + b a out

14. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf NOR layout b a out a b VDD GND tub ties

15. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf AOI/OAI gates n AOI = and/or/invert; OAI = or/and/invert. n Implement larger functions. n Pullup and pulldown networks are compact: smaller area, higher speed than NAND/NOR network equivalents. n AOI312: and 3 inputs, and 1 input (dummy), and 2 inputs; or together these terms; then invert.

16. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf AOI example out = [ab+c]’: symbolcircuit and or invert

17. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Pullup/pulldown network design n Pullup and pulldown networks are duals. n To design one gate, first design one network, then compute dual to get other network. n Example: design network which pulls down when output should be 0, then find dual to get pullup network.

18. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Dual network construction dummy a bc a b c

19. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Logic levels n Solid logic 0/1 defined by V SS /V DD. n Inner bounds of logic values V L /V H are not directly determined by circuit properties, as in some other logic families. logic 1 logic 0 unknown V DD V SS VHVH VLVL

20. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Logic level matching n Levels at output of one gate must be sufficient to drive next gate.

21. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Transfer characteristics n Transfer curve shows static input/output relationship—hold input voltage, measure output voltage.

22. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter transfer curve

23. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Logic thresholds n Choose threshold voltages at points where slope of transfer curve = -1. n Inverter has a high gain between V IL and V IH points, low gain at outer regions of transfer curve. n Note that logic 0 and 1 regions are not equal sized—in this case, high pullup resistance leads to smaller logic 1 range.

24. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Noise margin n Noise margin = voltage difference between output of one gate and input of next. Noise must exceed noise margin to make second gate produce wrong output. In static gates, t=  voltages are V DD and V SS, so noise margins are V DD -V IH and V IL - V SS.

25. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf CMOS Inverter: Transfer characteristic (Review) A: N: off P: linear B: N: saturated P: linear C: N: saturated P: saturated D: N: linear P: saturated E: N: linear P: off

26. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Device Models (Review) 26

27. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Delay n Assume ideal input (step), RC load.

28. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Delay assumptions n Assume that only one transistor is on at a time. This gives two cases: –rise time, pullup on; –fall time, pullup off. n Assume resistor model for transistor. Ignores saturation region and mischaracterizes linear region, but results are acceptable.

29. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Current through transistor n Transistor starts in saturation region, then moves to linear region.

30. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Capacitive load n Most capacitance comes from the next gate. n Load is measured or analyzed by Spice. n C l : load presented by one minimum-size transistor. C L =  (W/L) i C l

31. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Resistive model for transistor n Average V/I at two voltages: –maximum output voltage –middle of linear region n Voltage is V ds, current is given I d at that drain voltage. Step input means that V gs = V DD always.

32. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Resistive approximation

33. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Ways of measuring gate delay n Delay: time required for gate’s output to reach 50% of final value. n Transition time: time required for gate’s output to reach 10% (logic 0) or 90% (logic 1) of final value.

34. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter delay circuit n Load is resistor + capacitor, driver is resistor.

35. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Inverter delay with  model  model: gate delay based on RC time constant . n V out (t) = V DD exp{-t/(R n +R L )/ C L} n t f = 2.2 R C L n For pullup time, use pullup resistance.

36. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf  model inverter delay n 0.5 micron process: –R n = 6.47 k  –C l = 0.89 fF –C L = 1.78 fF n So –t d = 0.69 x 6.47E3 x 1.78E-15 = 7.8 ps. –t f = 2.2 x 6.47E3 x 1.78E-15 = 26.4 ps.

37. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Quality of RC approximation

38. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Power consumption analysis n Almost all power consumption comes from switching behavior. n Static power dissipation comes from leakage currents. n Surprising result: power consumption is independent of the sizes of the pullups and pulldowns.

39. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Other models n Current source model (used in power/delay studies): –t f = C L (V DD -V SS )/I d – = C L (V DD -V SS )/0.5 k’ (W/L) (V DD -V SS -V t ) 2 n Fitted model: fit curve to measured circuit characteristics.

40. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Power consumption circuit n Input is square wave.

41. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Power consumption n A single cycle requires one charge and one discharge of capacitor: E = C L (V DD - V SS ) 2. n Clock frequency f = 1/t. n Energy E = C L (V DD - V SS ) 2. n Power = E x f = f C L (V DD - V SS ) 2.

42. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Observations on power consumption n Resistance of pullup/pulldown drops out of energy calculation. n Power consumption depends on operating frequency. –Slower-running circuits use less power (but not less energy to perform the same computation).

43. Modern VLSI Design 4e: Chapter 3 Copyright  2008 Wayne Wolf Speed-power product n Also known as power-delay product. n Helps measure quality of a logic family. n For static CMOS: –SP = P/f = CV 2. n Static CMOS speed-power product is independent of operating frequency. –Voltage scaling depends on this fact.