Presentation on theme: "WTO Information technology symposium. "The Challenges ahead for the ITA with Converging Technologies and IC Manufacturing Techniques" Ray Foy – Intel Corp."— Presentation transcript:
WTO Information technology symposium. "The Challenges ahead for the ITA with Converging Technologies and IC Manufacturing Techniques" Ray Foy – Intel Corp. EMEA Customs & Licensing manager
Moores Law The number of transistors on a chip will double every months 1,000 10, ,000 1,000,000 10,000, ,000,000 1,000,000, Pentium 486 DX Pentium II Pentium III Pentium 4 1 Billion transistors before Million # of transistors
Interconnects Transistor Precision at the molecular and atomic levels. 23 masking layers. Some layers are thinner than a virus. Building an Integrated Circuit 1/10 th Thickness of Human Hair! ~ 60 days to manufacture
Process Trends: New Generation Every 2 Years Micron Nano-meter Nominal feature size Nanotechnology 130nm 90nm 70nm 50nm Gate Length Source: Intel
Processor Technology 1 nanometer = 1 billionth of a meter Silicon Process Technology 800nm600nm350nm250nm180nm130nm Transistors (Millions) Pentium ® Processor Pentium ® Pro Processor Pentium ® II Processor Pentium ® III Processor Pentium ® 4 Processor Itanium ® 2 Processor Smaller, Faster, Better, Cheaper
Average Transistor Price By Year Source: Dataquest/Intel12/ '68'70'72'74'76'78'80'82'84'86'88'90'92'94'96'98'00'02 $
Si Technology: Complexity Increasing Exponentially
Roadmap Trends: Summary More Speed per processors More memory integration More processors per core More transistors per processor. More complex manufacturing. Larger wafers Narrower circuits. The boundaries of physical science are the perennial challenge.
Today 2003/ / /2006 Chip Scale Stacked Package Folded Stacked Chip Scale Package Next generation Multichip Module Thru silicon and other advanced package options SIP Technologies: Stacked Die + Stacked Packages Stacked thin die +Packagingintegration +Packagingintegration
Microprocessor evolution – 1996 / 1997 Pentium® Pro Processor L2 Cache/ TAG/ Controller CPU & L1 Cache/ Controller Pentium (R) II Processor Dual die processor Cartridge package.
Multichip side by side in package
Vertical stacked ICs in package
Integrated Circuit stacking. Simple model – multi chip.
Multi- substrate / multi IC in package
Processor package x section
* data is run rate exiting the year. Source: Intel, *Other names and brands may be claimed as the property of others All CPU development on Dual/Multi-Core All CPU development on Dual/Multi-Core Moving from Chips/Computer to Computers/Chip Multi chips are already here.
Processor x section
Processor packaging – The problem with passives! Passive devices move classification outside HS 8542 Passive devices move classification outside HS 8542
The problem with passives. Integrated Passives (on silicon) –passive components on silicon, created in the mass to all intents and purposes indivisible. –Combined in multichip forms with other active ICs ALTERNATIVE TECHNOLOGY –TO CERAMIC / OTHER FORMS –SIGNIFICANT REDUCTION IN SIZE. –DRIVES FURTHER MINIATURISATION –All products of the semiconductor industry. BUT NOT ACCORDING TO THE CURRENT H.S.
BROADBANDEntertainment, E-Business, Services MEDIA Pre-Recorded Content Personal Media Personal Media BROADCASTServices,Entertainment Any Content 1, Any Place, Any Device, Any Time Digital Home Vision 1 As Authorized
Digital Home: All Devices and Content are going Digital
Innovation Demand COMPUTING COMMUNICATIONS All computing devices communicate All communication devices compute All enabled by silicon Convergence Vision Any Time, Anywhere, Any Device
Summary Miniaturising –Micron-scale to nano-scale. Functionalising. –Reduced size enables more functions in less space (all on silicon) –More integration / more complexity. Converging. (computing and comunications) –Developers put more optimum functionality for multiple application.
The Challenge The HS is unable to cope with the advance of technology. The problem is NOW! –All computing devices communicate –All communication devices compute –All enabled by silicon. Silicon circuitry and high density packaging serve: –energy conservation –Miniaturisation –Complex multifunctionality. The current HS should not be a limiter to ITA expansion.