Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std

Presentation on theme: "Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std"— Presentation transcript:

Figure 3–1 Standard logic symbols for the inverter (ANSI/IEEE Std
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–2 Inverter operation with a pulse input
Figure 3– Inverter operation with a pulse input. Open file F03-02 to verify inverter operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–3 Timing diagram for the case in Figure 3–2.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–4 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–5 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–6 The inverter complements an input variable.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–7 Example of a 1’s complement circuit using inverters.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–8 Standard logic symbols for the AND gate showing two inputs (ANSI/IEEE Std. 91-1984).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–9 All possible logic levels for a 2-input AND gate
Figure 3– All possible logic levels for a 2-input AND gate. Open file F03-09 to verify AND gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3– Example of AND gate operation with a timing diagram showing input and output relationships. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–11 Thomas L. Floyd Digital Fundamentals, 9e

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Figure 3–13 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–14 Boolean expressions for AND gates with two, three, and four inputs.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–15 An AND gate performing an enable/inhibit function for a frequency counter.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–16 A simple seat belt alarm circuit using an AND gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–17 Standard logic symbols for the OR gate showing two inputs (ANSI/IEEE Std. 91-1984).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–18 All possible logic levels for a 2-input OR gate
Figure 3– All possible logic levels for a 2-input OR gate. Open file F03-18 to verify OR gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3– Example of OR gate operation with a timing diagram showing input and output time relationships. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–20 Thomas L. Floyd Digital Fundamentals, 9e

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Figure 3–23 Boolean expressions for OR gates with two, three, and four inputs.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–24 A simplified intrusion detection system using an OR gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–25 Standard NAND gate logic symbols (ANSI/IEEE Std. 91-1984).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–26 Operation of a 2-input NAND gate
Figure 3– Operation of a 2-input NAND gate. Open file F03-26 to verify NAND gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–27 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–28 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–29 Standard symbols representing the two equivalent operations of a NAND gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–30 Thomas L. Floyd Digital Fundamentals, 9e

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Figure 3–33 Standard NOR gate logic symbols (ANSI/IEEE Std. 91-1984).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–34 Operation of a 2-input NOR gate
Figure 3– Operation of a 2-input NOR gate. Open file F03-34 to verify NOR gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–35 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–36 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–37 Standard symbols representing the two equivalent operations of a NOR gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–38 Thomas L. Floyd Digital Fundamentals, 9e

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Figure 3–41 Standard logic symbols for the exclusive-OR gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–42 All possible logic levels for an exclusive-OR gate
Figure 3– All possible logic levels for an exclusive-OR gate. Open file F03-42 to verify XOR gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–43 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–44 Standard logic symbols for the exclusive-NOR gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–45 All possible logic levels for an exclusive-NOR gate
Figure 3– All possible logic levels for an exclusive-NOR gate. Open file F03-45 to verify XNOR gate operation. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–46 Example of exclusive-OR gate operation with pulse waveform inputs.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–47 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–48 An XOR gate used to add two bits.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–49 Basic concept of a programmable AND array.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–50 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–51 The programmable fuse link.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–52 The programmable antifuse link.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–53 A simple AND array with EPROM technology
Figure 3– A simple AND array with EPROM technology. Only one gate in the array is shown for simplicity. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–54 Basic concept of an AND array with SRAM technology.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–55 Setup for programming a PLD in a programming fixture (programmer).
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–56 Programming setup for reprogrammable logic devices.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–57 Examples of design entry of an AND gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–58 Simplified illustration of in-system programming via a JTAG interface.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–59 Simplified block diagram of a PLD with an embedded processor and memory.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3– Typical dual in-line (DIP) and small-outline (SOIC) packages showing pin numbers and basic dimensions. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–61 Pin configuration diagrams for some common fixed-function IC gate configurations.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3– Logic symbols for hex inverter (04 suffix) and quad 2-input NAND (00 suffix). The symbol applies to the same device in any CMOS or TTL series. Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–63 Thomas L. Floyd Digital Fundamentals, 9e

Figure 3–64 The LS TTL NAND gate output fans out to a maximum of 20 LS TTL gate inputs.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–65 The partial data sheet for a 74LS00.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–66 The partial data sheet for a 74HC00A.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–67 The effect of an open input on a NAND gate.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–68 Troubleshooting a NAND gate for an open input.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

Figure 3–69 Troubleshooting a NOR gate for an open output.
Thomas L. Floyd Digital Fundamentals, 9e Copyright ©2006 by Pearson Education, Inc. Upper Saddle River, New Jersey All rights reserved.

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