Presentation on theme: "ECE 6466 “IC Engineering” Dr. Wanda Wosik"— Presentation transcript:
1 ECE 6466 “IC Engineering” Dr. Wanda Wosik Chapter 1Introduction to Technology and DevicesSilicon VLSI Technology Fundamentals, Practice and Modeling by J. D. Plummer, M. D. Deal, and P. B. GriffinUH; F2014
2 Chapter 1: INTRODUCTION • This course is basically about silicon chip fabrication, the technologies used tomanufacture ICs.• We will place a special emphasis on computer simulation tools to helpunderstand these processes and as design tools.• These simulation tools are more sophisticated in some technology areas than inothers, but in all areas they have made tremendous progress in recent years.• 1960 and 1990 integrated circuits.• Progress due to: Feature size reduction - 0.7X/3 years (Moore’s Law).Increasing chip size - ≈ 16% per year.“Creativity” in implementing functions.
3 Evolution of the Silicon Integrated Circuits since 1960s Increasing: circuit complexity, packing density, chip size, speed, and reliabilityDecreasing: feature size, price per bit, power (delay) product1960s1990s
5 Device Scaling Over Time ~13% decrease in feature size each year (now: ~10%)Era of Simple Scaling~16% increase in complexity each year (now:6.3% for µP, 12% for DRAM)Cell dimensions0.25µm in 1997Scaling + Innovation(ITRS)InventionAtomic dimensions• The era of “easy” scaling is over. We are now in a period wheretechnology and device innovations are required. Beyond 2020, newcurrently unknown inventions will be required.
17 • Assumes CMOS technology dominates over entire roadmap. Trends in Increasing Integration Scale of Circuits Past, Present, and Future ICsITRS at (2003 version update) – on class website.• Assumes CMOS technology dominates over entire roadmap.• 2 year cycle moving to 3 years (scaling + innovation now required).• 1990 IBM demo of Å scale “lithography”.• Technology appears to be capable of making structures much smaller thancurrently known device limits.
18 Historical Perspective • Invention of the bipolartransistor , Bell Labs.• Shockley’s “creative failure”methodology• Grown junction transistortechnology of the 1950s
19 Building Blocks of Integrated Circuits Bipolar Transistors(BJT) and Metal Oxide Semiconductor Field Effect Transistors (MOSFET) with n- and p-type channels.• Alloy junction technology of the 1950s.Fabrication of Bipolar Transistors in the 1950sGe used as a crystal, III and V group atoms used as dopants3rd groupAl wiresp-n-p transistorExposed junctions had degraded surface properties and no possibility of connecting multiple devices
20 Evolution of the Fabrication Process The Mesa Design of Bipolar TransistorsBell Lab, 1957, Double Diffused ProcessContacts alloyedSolid state B diffusionMesa etchedSolid state P diffusionAdvantage: Connection of multiple devices but no ICsDisadvantage: Degradation by exposed junctions at the surface
21 • The planar process (Hoerni - Fairchild, late 1950s).• First “passivated” junctions.• Basic lithography processwhich is central to today’schip fabrication.
22 Evolution of the Fabrication Process: The Planar Design of Bipolar Transistors Beginning of the Silicon Technology and the End of Ge devicesImplementation of a masking oxide to protect junctions at the Si surfaceOxidation possible for Si not good for GeLithography to open window in SiO2Boron diffusionSiO2MaskPhosphorus diffusion through the oxide maskOxidation and outdiffusionThe planar process of Hoerni and Fairchild (1950s)
23 Photolithography used for Pattern Formation Beginning of Integrated Circuits in 1959Kilby (TI) and Noyce (Fairchild Semiconductors)Photolithography used for Pattern FormationSensitive to lightDurable in etching• Basic lithography processwhich is central to today’schip fabrication.
24 Alignment of Layers to Fabricate IC Elements • Lithographic process allows integration of multiple devices side by side on a wafer.Bipolar Transistor and resistors made in the base regionAccuracy of placement ~1/4 to 1/3 of the linewidth being printedBJTB0VVccCEResistorBaseR=L/W•RsResistorEmitterContact to collectorCollector
25 Schematic Cross-Section of Modern CMOS Integrated Circuit with Two Metal Levels IC is located at the surface of a Si wafer (~500µm thick)InterconnectM2OXIDEViaM1SilicideTiNOxide IsolationPMOSNMOS
26 Modern IC with a Five Level Metallization Scheme. Planarization
27 Computer Simulation Tools (TCAD) • Actual cross-section of a modernmicroprocessor chip. Note themultiple levels of metal andplanarization. (Intel website).Computer Simulation Tools (TCAD)•Most of the basic technologies in silicon chip manufacturing can now be simulated.Simulation is now used for:• Designing new processes and devices.• Exploring the limits of semiconductor devices and technology (R&D).• “Centering” manufacturing processes.• Solving manufacturing problems (what-if?)
28 • Simulation of anadvanced localoxidation process.• Simulation ofphotoresist exposure.