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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals.

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Presentation on theme: "DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 1 International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals."— Presentation transcript:

1 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July International Technology Roadmap for Semiconductors 2005 ITRS/ORTC Product Model Proposals For Public 07/13/05 Conference (based on Rev1Kc, 07/12/05)

2 ORTC Overview ITRS Proposals Recommendation for one standard TWG table technology trend header –Presently continue to use DRAM stagger-contacted M1 as typical industry lithography driver – UNCHANGED from the 2003/2004 Roadmap Update –Remove ITRS single-product node label emphasis, to minimize industry guidance confusion; as we transition to product-oriented technology trend drivers and cycles* ORTC Table 1a,b - adjusted to Proposed Japan (STRJ) MPU/ASIC M1 Half- Pitch Trend –Stagger-contacted, same as DRAM –2.5-year Technology Cycle* (.5x/5yrs) –180nm/2000; 90nm/2005; 45nm/2010(equal DRAM) –Then continue on a 3-year Technology Cycle*, equal to DRAM ORTC Table 1a,b - added Proposed STRJ Flash Poly (Un-contacted dense lines) –2-year Technology Cycle* (0.5x/4yrs) –180nm/2000; 130nm/2002; 90nm/2004; 65nm/2006 –Then 3-year Technology Cycle* 1 year ahead of DRAM ORTC Table 1a,b – adjusted MPU/ASIC Printed Gate Length to FEP and Litho TWG agreement for ratio relationship to Final Physical Gate Length, which remains UNCHANGED from the 2005 ITRS targets (3-year cycle* after 2005) TWG table Product-specific technology trend driver header items to be added to individual TWG tables from ORTC Table 1a&b Chip Size Models connected to proposals and historical trends, incl. new Flash Model –Function Size [Logic Gate; SRAM Cell; Dram Cell; Flash Cell (SLC, MLC)] –Functions/Chip [Flash; DRAM; High Performance (hp) MPU; Cost Perf. (cp) MPU] –Chip Size [hp MPU; cp MPU; DRAM; Flash] *Note: Cycle = time to 0.5x linear scaling every two cycle periods ~ 0.71x/ cycle DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

3 3 Source: 2003 ITRS - Exec. Summary Fig /2004 ITRS Definition of the Half Pitch - WAS [DRAM half-pitch determines the 2003 ITRS node] Metal Pitch Typical DRAM Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 Poly Pitch Typical MPU/ASIC Un-contacted Poly MPU/ASIC Poly Silicon ½ Pitch = MPU/ASIC Poly Pitch/2 Typical MPU/ASIC Contacted Metal 1 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Metal 1 (M1) Pitch

4 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Definition of the Half Pitch – IS [No single-product node designation; DRAM half-pitch still litho driver; however, other product technology trends may be drivers on individual TWG tables] Metal Pitch Typical DRAM/MPU/ASIC Metal Bit Line DRAM ½ Pitch = DRAM Metal Pitch/2 MPU/ASIC M1 ½ Pitch = MPU/ASIC M1 Pitch/2 Poly Pitch Typical flash Un-contacted Poly FLASH Poly Silicon ½ Pitch = Flash Poly Pitch/ Lines

5 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Production Ramp-up Model and Technology Node Volume (Parts/Month) 1K 10K 100K Months M 10M 100M Alpha Tool DevelopmentProduction Beta Tool Production Tool First Conf. Papers First Two Companies Reaching Production Volume (Wafers/Month) K 20K 200K Source: 2003 ITRS - Exec. Summary Fig 2 Fig 2 [UNCHANGED]

6 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July hp22hp32hp45hp65hp [Actual] Year of Production hp130 Technology Node (nm) WAS: 2003 ITRS Technology Nodes: 3-year cycle* 3-Year Technology Cycle 2-Year Technology Cycle [ actual] Note: Faster introduction of half-poly pitch from Flash is expected; and Doubling of transistors every 2 years from MPU/ASIC is expected. * Cycle Time = one-half of the time to reach a technology trend reduction to 0.5x Source: 2003 ITRS - Exec. Summary

7 Note: Faster introduction of half-poly pitch from Flash is expected; Doubling of transistors every 2 years from MPU/ASIC is expected 2005 ITRS Flash Poly Half-Pitch Technology: 2.0-year cycle until 1yr ahead of 3-Year Technology Cycle 2-Year Technology Cycle [98-06 ] Year of Production Technology - Uncontacted Poly H-P (nm) [Actual] [Actual] ITRS MPU M1 Half-Pitch Technology: 2.5-year cycle; then equal Year of Production Technology - Contacted M1 H-P (nm) [July 08][July 02] [130]180[ 65] Year Technology Cycle 3-2-Yr Cycle] 3-Year Technology Cycle 14 IS: 2005 (05-20) ITRS Technology Trends DRAM M1 Half-Pitch : 3-year cycle 3-Year Technology Cycle 2-Year Technology Cycle [98-04] Year of Production Technology - Contacted M1 H-P (nm) [Actual] [Actual] DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

8 8.71x/2.5yrs Historical.71x/3yrs 2005 ITRS Product Technology Trends Past Future ITRS Range [Cross DRAM 65nm/ year ahead after that] [Equal DRAM 45nm/2010] [GLpr IS = x GLph WAS, which is unchanged from 2003/04 ITRS, but under discussion by FEP, PIDS, Litho, and Design TWGs for CD-control red limits] [Unchanged from 2003 ITRS].71x/2yrs.71x/3yrs GLpr / GLph = Ratio DRAM Survey Update: - DRAM (H-P unchanged) Flash: Japan/STRJ MPU: Japan/STRJ

9 Past Future ITRS Range DRAM IS: 8f 2 -> 6f 2 / f 2 ~ 29f 2 ~ 320f 2 Flash 28f 2 -> 4f 2 [WAS: 2003 ITRS] [IS: 2005 ITRS] Note: f = product-related Half-Pitch Feature Size; A = product-related Design Factor; n = # transistors per SRAM cell or MPU Logic Gate; Af 2 = Function Size; Af 2 /n = SRAM Cell or Logic Gate Transistor Size Note for Flash: SLC = Single-Level-Cell Size MLC = Multi-Level-Cell (Electrical Equivalent) Cell Size DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

10 10 Moores Law After 40 years (functions per chip) Pentium® Processor 486 DX Processor 386 Processor 286 Pentium® II Processor Pentium® III Processor Itanium® Processor Pentium® 4 Processor Itanium® 2 Processor 2X/2YR 2X/1YR 2X/2YR Source: Intel® Corp.

11 Chip Size Trends – 2005 ITRS Functions/Chip Model Proposal IS (WAS) Past Future ITRS Range Average Industry Moores Law 2x Functions/chip Per 2 years Production, Affordable Chip Size**) ** Affordable Production Chip Size Targets: DRAM, Flash < 145mm 2 hp MPU < 310mm 2 cp MPU < 140mm 2 ** Example Chip Size Targets: 1.1Gt P07h intro in 2004/620mm prod in 2007/310mm 2 ** Example Chip Size Targets: 0.39Gt P07c intro in 2004/280mm prod in 2007/140mm 2 MPU ahead or = Moores Law 2x Xstors/chip Per 2 years Thru 2010 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

12 Past Future ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS DRAM & Flash (NEW) Model IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

13 Past Future ITRS Range Chip Size Trends – 2003/04 vs.2005 ITRS Flash (NEW) Model IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

14 Past Future ITRS Range Chip Size Trends – 2005 ITRS MPU Model Proposal IS DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

15 Summary DRAM Model stagger-contacted M1 is unchanged from 2003/2004 Update ITRS (single-Node reference removed) MPU Revised M1 to stagger-contact half-pitch (same as DRAM) and 2.5-year cycle* through 2010, then 3-year cycle* same as DRAM New Flash Model Added for un-contacted poly half-pitch and equal to DRAM contacted, but continues on 2-year cycle* to 1 year ahead of DRAM in 2006, then 3-year cycle* same as DRAM Printed MPU/ASIC Gate Length adjusted to new FEP and Litho TWGs ratio agreement, but Physical GL unchanged and on 3-year cycle* beginning 2005 Historical chip size models connected to new Product model proposals, including design factors, function size, and array efficiencies Average industry product Moores Law met or exceeded throughout ITRS timeframe [* ITRS Cycle definition = time to.5x linear scaling every two cycle periods] DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

16 16 Backup

17 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Generic ITRS Table Header Technology Trend Proposal: Optional (from ORTC Table 1a&b) TWG Table Product-Specific Technology Trend Proposals:


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