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Performance estimates for the various types of emerging memory devices Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)

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Presentation on theme: "Performance estimates for the various types of emerging memory devices Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)"— Presentation transcript:

1 Performance estimates for the various types of emerging memory devices Victor Zhirnov (SRC) and Ramachandran Muralidhar (Freescale)

2 2 Rationale u We seek to identify fundamental physical limits for various types of memory devices v Best projections for scaling n e.g. no consolidated theory has been developed for Flash scaling Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001

3 3 Attributes of an ideal memory u Nonvolatility with long retention (e.g.. > 10 years) u High density u Low power u In-system rewrittability u Fast read/write u High endurance (the number of erase/write/read cycles) u Integration with CMOS logic: v Matching operational voltage v Matching time (speed) Focus of this talk

4 4 Three Components of Memory Device u Three equally important components of memory systems: n Memory cell (Physics of of Write/Erase/Program) n Sensing (Physics of Read/Sense) n Wires (implication of the physics of Write and Read to accessibility) n The key of a cells usefulness is whether the cell can be written to and read from without affecting the surrounding cells. Focus of this analysis

5 5 ERD ITWG Memory Discussion 10:45 Quantitative estimates of performance for the various types of memories Engineered barrier Muralidhar and Zhirnov Ferroelectric Waser NanoelectromechanicalZhirnov Fuse/AntifuseWaser and Akinaga 12:00-12:30 Lunch IonicWaser and Akinaga Electronic EffectsWaser and Zhirnov MacromolecularZhirnov Molecular Waser 1:30 Break - Adjourn Memory Discussion

6 6 Charge-based Memories AB e- Control Requirements: 1) Efficient charge injection during programming 2) Suppressed back-flow of charge in store/read modes 3) Efficient erase 4) Min. charge/bit: q=e=1.6x10 -19 Q DRAM/SRAM Floating Gate Memory SONOS

7 7 Barrier-less Ohmic Transport: The most efficient injection, but… Write Store … difficult retention EbEb What is the minimum barrier height for the charge- based NVM? Example: DRAM Charge-based memory is a two-barrier system

8 8 What is the minimum barrier height for the charge-based NVM? Store Problem: In Si devices E bmax { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/2/696795/slides/slide_8.jpg", "name": "8 What is the minimum barrier height for the charge-based NVM.", "description": "Store Problem: In Si devices E bmax

9 9 Charge injection problem in high- barrier systems BUT: Barrier formed by an insulating material (large E b ) cannot be suppressed) – charge transport in the presence of barriers: Non-ohmic charge transport High-barriers are needed for Non-volatile memory Tunneling Hot-electron injection Newly proposed nanomechanical DRAM addresses this problem

10 10 Two-barrier charge-based NVM C. Y. Chang, S. M. Sze (Eds.), ULSI Devices (John Wiley & sons 2000) Floating gate memory M. H. White,Y. Yang, A. Purwar, and M. L. French, IEEE Trans. Compon. Packag. and Manufact. Technol. Pt A 20 (1997) 190 SONOS memory

11 11 Floating gate memory: WRITE and STORE modes V Control gate Floating gate FET channel 0 V leakage WRITE STORE

12 12 V Floating gate cell: Write – triangle barrier Retention – trapezoidal barrier We need to create an asymmetry in charge transport through the gate dielectric to maximize the I write /I ret ratio The asymmetry in charge transport between WRITE and STORE modes is achieved through different shape of barrier (triangle vs. trapezoidal)

13 13 Floating Gate Cell Retention and WRITE characteristics Ideal case Retention: direct tunneling k B T/e < V stored E b Si/SiO 2 : E b =3.1 V, V WSiO2 >6.2 V For lower WRITE voltage E b should be decreased: E bmin =1.5 eV V min >3 V

14 14 The Industry Standard Flash Memory Cell Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001

15 15 Parameters Projections for n-FG This Analisis SiO 2, E b =3.1eV v V min >6.8 V (slow operation) v V~12 V (ms operation) a min >5.4 nm (reliability issue) v L min >15 nm (gate stack AR, FET issues…) u Optimized FG memory cell v E b =1.5 eVHfO 2 v V min >3 V (slow operation) v V~4 V (ms operation) a min ~6.3 nm v L min ~12 nm Standard FLASH SiO 2 E b =3.1eV v - v 10-20 V v ~6 nm v ~18 nm Flash Memories, P. Cappelletti et al (Eds), Kluwer 2001 Nanocrystals, Charge trapping High-K !

16 16 Parameters Projections for n-FG SiO 2 HfO 2 ~2x10 -18 F~6x10 -18 F 30 1.43x10 -17 J7.2x10 -18 J Lower bound (slow operation) 3x10 -16 J V~12 V (ms operation) Statistical issue

17 17 Materials Challenges of symmetrically graded barrier : vs. K =0.2-0.5 Kramers-Kronig relation K 1 { "@context": "http://schema.org", "@type": "ImageObject", "contentUrl": "http://images.slideplayer.com/2/696795/slides/slide_17.jpg", "name": "17 Materials Challenges of symmetrically graded barrier : vs.", "description": "K =0.2-0.5 Kramers-Kronig relation K 1

18 18 Symmetrically graded (crested) barrier V=0 E b =2 V V=1 V E b =1.5 V E b =1 V V=2 V V=2*E b =4 V E b =0 Likharev, K.K., Single-electron devices and their applications, Proc. IEEE 87 (1999) 606-632 Uses a stack of insulating materials to create a special shape of barrier enabling effective transport into/from the storage node V w ~8 V

19 19 Engineered tunnel barrier memory Likharev

20 20 Charge injection problem in high- barrier systems Hot-electron injection More accurate estimates based on Shockleys lucky electron model TBD

21 21 Summary on Floating Gate Memory u Operation voltage cannot be small (e.g. V>6 V for Si/SiO2) u V-t dilemma Question: How to reduce the write voltage for the tunneling based memories? Answer: v To perform write operation in direct tunneling mode n In principle, the voltage can be as small as wished n There are two problems though: 1) Very slow writing 2) Very small retention

22 22 SONOS M. H. White,Y. Yang, A. Purwar, and M. L. French, IEEE Trans. Compon. Packag. and Manufact. Technol.Pt A 20 (1997) 190 For lower voltage operation of floating charge memory, direct tunneling needs to be used for charge injection. Tunnel insulator must be very thin for reasonably small WRITE time We now have a problem of of how to create the asymmetry between WRITE and STORE charge transport paths

23 23 SONOS : Write and Retention Write: Direct tunneling: V tun <3.1 V, a write =d 1 a ret d1d1 d2d2 d3d3 a ret >a write The asymmetry between WRITE and STORE charge transport paths is achieved by different path length X. Wang, et al, IEEE Trans. El. Dev. 51 (2004) 597 Retention: BUT: We now have a problem of of how to create the symmetry between WRITE and ERASE operations Retention?? ? Erase???

24 24 Solutions to improve characteristics of charge-trapping memory? u Alternative dielectrics, e.g. with lower barrier height, high K u Is it possible to control/engineer the trap sites in silicon nitride: concentration, distribution, position, energy levels? X. Wang, et al, IEEE Trans. El. Dev. 51 (2004) 597 HfO 2 Ta 2 O 5 ERM

25 25 Conclusion on ultimate charge- based memories u All charge-based memories suffer from the barrier issue: v High barriers needed for long retention do not allow fast charge injection v It is difficult (impossible?) to match their speed and voltages to logic n Voltage-Time Dilemma Non-charge-based NVMs?

26 Electronic Effects

27 27 Electronic Effects Memory u 1) Charge injection and trapping v Simmons and Verderber, New conduction and reversible memory phenomena in thin insulating films u 2) Mott transition u 3) Ferroelectric polarization effects.

28 28 Simmons-Verderber theory u Unipolar/non-polar switching v Charging trapes in insulator u Forming process is critical v Strongly suggestive of positive ion injection into insulator 2 ns 100 ns WriteErase I

29 29 Energy Diagram, V=0

30 30 Energy Diagram, V>0 V< 0 (energy of localized levels) V> 0 (energy of localized levels)

31 31 Memory effect: Charge injection

32 32 Memory effect: Charge travel

33 33 Memory effect: Charge storing

34 34 Memory effect: Charge erase

35 35 Switching (Erase) time estimate Quantum harmonic Oscillator N~10 19 cm -3 s~2 nm E trap ~1 eV

36 36 Switrching time

37 37 Thickness scaling N~10 19 cm -3 ~9 nm L min ~20nm L

38 38 Scaling limits depend on materials properties N~10 19 cm -3 s~2 nm E trap ~1 eV ~9 nm L min ~20nm t min ~60ns

39 39 Macromolecular Memory u Polymer memory u Organic memory u Different mechanisms proposed v Filaments v Ionic v Charged traps in polymer etc u Verbakel et al. Reproducible resistive switching in nonvolatile organic memories, APL 91 (2007) v Resistive switching in organic memories can be due to the presence of a native oxide layer at an aluminum electrode


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