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DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 1 2005 updates to the Lithography chapter of the ITRS Lithography International Technology.

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Presentation on theme: "DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005 1 2005 updates to the Lithography chapter of the ITRS Lithography International Technology."— Presentation transcript:

1 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July updates to the Lithography chapter of the ITRS Lithography International Technology Working Group July 2005

2 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Lithography ITWG chair persons and co- chair persons for 2005

3 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Summary of 2004 Lithography Chapter Updates Defined more specific criteria for evaluating near-term potential solutions Stronger emphasis on difficult challenges related to immersion lithography Continued emphasis on challenges for implementing cost-effective post-optical lithography solutions

4 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Proposed 2005 Lithography Updates CD control and line edge roughness (LER) –Agreed along with Design, PIDS and FEP TWGs to increase CD tolerance to 12% CD control for MPU gates is still red (red starts at <4 nm 3 ) –Agreed with FEP TWG on larger printed CD in resist physical gate length and 75%/25% variance allocation for lithography and etch, respectively –Proposed new definition of LWR and LER that better accounts for metrology, transistor and interconnect performance –Increased bias between size in resist and after etch for contacts Significantly tighten overlay tolerances from 35% to 20% of DRAM ½ pitch Add lithographic tool field width and length Update potential solutions Update colors and values in mask and resist tables Proposal only; Not for publication

5 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July ITRS lithography requirements are challenging Update Proposal only; Not for publication

6 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July updates to the chapter text Table showing progression of low k 1 methods DFM section to complement content in Design chapter Automatic process control (APC) detail Cost of ownership factors and throughput factors described in text Brief text about number of critical levels Proposal only; Not for publication

7 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Criteria for potential solutions All infrastructure (masks, tools, resist,…) needs to be in place to meet the ramp for the specified node Technology must be planned to be used by IC makers in at least two geographical regions –For N+3 and later nodes with black coloring, the requirement to have more than one region support is not applicable Technology should be targeting leading edge critical layer needs Consideration (not a requirement): 100 tools worldwide over the life of that tool generation (not for each node)

8 2004 Lithography exposure tool potential solutions Notes: RET and lithography friendly design rules will be used with all photon projection lithography solutions, including with immersion; therefore, it is not explicitly noted. Technology Node hp90hp65hp32hp16hp22hp45 Research Required Development Underway Qualification/ Pre-Production Continuous Improvement DRAM Half-pitch (dense lines) Technology Options at Technology Nodes (DRAM Half-Pitch, nm) nm nm 193i with water PEL? (decision by Sept.) 32 EUV 193i with other fluids and lens material Innovative 193i with water Imprint, ML Innovative technology Innovative EUV, imprint, ML i with water 193i with other fluids EUV, ML2 EPL/PEL? (decision by Sept. 2005) RET = Resolution enhancement technology LFD = Lithography friendly design rules ML2 = Maskless lithography Lithography Potential Solutions Possible 2005 Update from Spring iTWG EUV Innovative 193 nm immersion Imprint,ML2, innovative technology Proposal only; Not for publication DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

9 Acknowledge: Kameyama, Nikon History of ITRS Litho Potential Solutions 2001 Edition ML2 EPL EUV IPL PEL PXL Innovation 193nm+PSM 248nm+PSM 157nm+PSM Imprint 2003 Edition PEL ML2 EPL Innovation EUV +RET 157nm+ RET+LFD+Immersion 193nm+ RET+LFD+Immersion Innovation 2005 Proposal 193nm PEL ML2 EPL ? EUV Imprint 193nm Immersion ? 193i w/ other fluids

10 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Significant changes to potential solutions in nm immersion with water and other fluids expected to be primary technology through 45nm and perhaps 32nm ½ pitch with new lens materials 157nm no longer seen as potential solution EUV remains most likely next generation lithography (NGL) with possible use starting at 45nm ½ pitch and primary solution for 32nm and 22nm ½ pitch Electron projection and proximity electron not as probable as in 2004 Maskless lithography remains as potential solution starting at 45nm ½ pitch Imprint extended to cover 32nm through 16nm ½ pitch Proposal only; Not for publication

11 Resolution improvement by immersion Silicon Wafer Photoresist Lens Liquid Photoresist Silicon Wafer Lens N water = 1.44

12 Enabling NA > 1.3 Water Immersion Fluid Final Lens Element Resist Numerical aperture High Index Fluid Plano CaF 2 or SiO 2 High Index Lens Material Curved Final Element Existing Platforms High Index Resist Earlier increase in index of fluid and/or resist yields process latitude improvement Acknowledge: Andrew Grenville

13 Extreme Ultraviolet Lithography (EUV) Laser nm) Ref. (%) 40 All optics surfaces coated with multilayer reflectors ( layer pairs, each layer approx /4 thick, Control ~0.1 Å) Wafer Condenser Optics 4X Reduction Optics EUV imaging with ultrathin resist (UTR) Laser Produced Plasma Reflective Reticle Ring Field Illumination Scanning mask and wafer stages Flat, square mask with multilayers Reflective Optical Surfaces are Aspheric with Surface Figures & Roughness < 3 Å = 13.5 nm 35nm 70nm

14 Present mode of operation for circuit design and fabrication Organizational, corporate cultural and geographical barriers Designers Wafer fab Circuit architecture Masks Layout Test data Packaged IC Device models Design rules

15 New mode of operation with design for manufacturing (DFM) practices Designers Wafer fab Circuit architecture Masks optimized based on design intent Layout with critical paths Packaged IC Device models Design rules Statistical timing optimization Process variation distributions Known contours of CD, topography or overlay error with mfg. process Test data

16 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Proposed Changes to ITRS Resist Tables Re-evaluated all colors in resist tables –Input from resist suppliers toward matching capability (colors) with requirements (numbers) –Re-examined defect size in resist films Back surface particle levels updated based on FEP values Improved LWR/LER definition and values Proposal only; Not for publication

17 Importance of Line Edge and Width Roughness Line Edge Roughness (LER) (High frequency roughness) –Can affect dopant concentration profiles –Probably affects interconnect resistance Line Width Roughness (LWR) (Mid-frequency roughness) –Leakage of transistors affected –Affects device speed of individual transistors –Leads to IC timing issues Ben Bunday, SEMATECH Example: poly-silicon line Edge assignment from SEM algorithm Spatial frequency (nm -1 ) LER LWR

18 DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July Fringing Field Disorder n+ Gate Rough Gate Edge Junction edge fluctuations Gate-SD Overlap disorder Halo fluctuations Poly s Eric Verret, Aaron Thean and Jonathan Cobb; Freescale Semiconductor Areas of potential device impact Front end patterning –LWR after etch is what matters, not LWR in resist – LWR affects leakage current more strongly than drive current Ioff ( nA / um on log scale ) Ion ( uA / um ) L=50nm L=40nm L=32nm Nominal device w/o LER 7nm 3 LER

19 Scaling relations for Table 77 and 79 ItemValue (in nm) where becomes: YellowRed CD = Physical gate width = 0.4 DRAM ½ pitch4020 Overlay = 20% DRAM ½ pitch 2013 Minimum linewidth in resist = physical gate5025 Contact size after etch = ½ pitch8560 Contact in resist = 1.1 contact after etch8560 CD control for DRAM = 13.5% sqrt(0.75) DRAM ½ pitch74 CD control for MPU/ASIC = 74 12% sqrt(0.75) MPU/ASIC M1 contacted ½ pitch Mask nominal image size = MAG resist linewidth SRAF feature is ½ of mask nominal image Mask Min. Primary Feature Size = Mask nominal image size Mask CD control = CD MAG sqrt(0.75) 4% / MEEF 85 Placement = Overlay MAG 15%1410 Defect size = DRAM ½ Pitch MAG / Linearity = 3.8% DRAM ½ pitch MAG1510 CD mean-to-target = 2% DRAM ½ pitch MAG74 Absorber LER = Min. CD MAG 3%74 Blank flatness 1/NA 2 (250nm in 2007) Data volume = 2 increase / node (260 GB in 2004) GB Proposal only; Not for publication Update DRAFT – Work In Progress - NOT FOR PUBLICATION 13 July 2005

20 20 Summary 193nm immersion and EUV lithography are promising candidate technologies for 45-nm and 32-nm half-pitch patterning –Significant challenges remain in developing either technology to provide a timely, economical manufacturing solution Innovations in immersion, EUV and new techniques such as ML2 and imprint might become prevalent starting at 32-nm ½ pitch Maintaining ±10% CD control doesnt appear to be possible, and ±12% adopted, ±12% still difficult to achieve More stringent overlay tolerances important for manufacturing of memory circuits Measuring and controlling LWR and LER becoming increasingly important Increasing integration of design, modeling, lithographic resolution enhancement techniques and extensive metrology will be needed to maintain expected circuit performance


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