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ECE 331 – Digital System Design Power Dissipation and Propagation Delay.

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Presentation on theme: "ECE 331 – Digital System Design Power Dissipation and Propagation Delay."— Presentation transcript:

1 ECE 331 – Digital System Design Power Dissipation and Propagation Delay

2 ECE 331 - Digital System Design2 Power Dissipation

3 ECE 331 - Digital System Design3 Power Consumption Each integrated circuit (IC) consumes power P T = P S + P D – P T = total power consumed by IC – P S = static or quiescent power consumption – P D = dynamic power consumption

4 ECE 331 - Digital System Design4 Power Dissipation Static Power Consumption

5 ECE 331 - Digital System Design5 Static Power Consumption P S = V CC * I CC – V CC = supply voltage – I CC = quiescent supply current – P S = static power consumption I CC and V CC are specified in the datasheet for integrated circuit (IC). P S for CMOS devices is very small

6 ECE 331 - Digital System Design6 Static Power Consumption Example: Calculate the static power dissipation for a 74LS00 2-input NAND gate.

7 ECE 331 - Digital System Design7 Example: 74LS00 (TTL)

8 ECE 331 - Digital System Design8 Example: 74LS00 (TTL) Supply Voltage  4.75 V <= V CC <= 5.25 V Supply Current  High Output: I CCmax = 1.6 mA  Low Output:I CCmax = 4.4 mA Maximum static power consumption  High Output:P S = 8.4 mW  Low Output:P S = 23.1 mW

9 ECE 331 - Digital System Design9 Example: 74LS00 (TTL) Example: (continued) – Duty Cycle Clock signal typically has 50% duty cycle – P S = P S_high * t high + P S_low * t low P S_high = 8.4 mW P S_low = 23.1 mW Assume 50% duty cycle (high / low half the time) P S = 8.4 mW * 0.5 + 23.1 mW * 0.5 = 15.8 mW Assume 60% duty cycle (high 60% of the time) P S = 8.4 mW * 0.6 + 23.1 mW * 0.4 = 14.28 mW

10 ECE 331 - Digital System Design10 Static Power Consumption Example: Compare the static power dissipation of the 74LS00 NAND gate with that of the 74HC00 NAND gate.

11 ECE 331 - Digital System Design11 Example: 74HC00 (CMOS)

12 ECE 331 - Digital System Design12 Example: 74HC00 (CMOS) P S = V CC * I CC Supply Voltage  V CC = 6.0 V Supply Current  I CC = 20  A Maximum static power consumption  P S = 6.0 V * 20  A = 120  W

13 ECE 331 - Digital System Design13 Power Dissipation Dynamic Power Consumption

14 ECE 331 - Digital System Design14 Dynamic Power Consumption TTL – P D ~= 0 W CMOS – P D != 0 W – Movement of charge into and out of device capacitances is used to determine dynamic power consumption.

15 ECE 331 - Digital System Design15 Dynamic Power Consumption CMOS – Charge is stored in the internal (C PD ) and load (C L ) capacitances C PD = power dissipation capacitance (internal) C L = capacitance of load and wires (external) – Capacitances are in parallel C T = total capacitance = C PD + C L – Stored charge (Q) Q T = C T * V DD = (C PD + C L ) * V DD

16 ECE 331 - Digital System Design16 Dynamic Power Consumption CMOS (continued) – Charge is moved on each output transition Output transition from high to low and low to high – Movement of charge = current I AVG = (C PD + C L ) * V DD * f T f T = output frequency (i.e. # of transitions per second) – P D = I AVG * V DD = (C PD + C L ) * V 2 DD * f T

17 ECE 331 - Digital System Design17 Dynamic Power Consumption Example: Calculate the dynamic power consumption for a 74HC00 2-input NAND gate.

18 ECE 331 - Digital System Design18 Example: 74HC00 (CMOS)

19 ECE 331 - Digital System Design19 Example: 74HC00 (CMOS)

20 ECE 331 - Digital System Design20 Dynamic Power Consumption Example: 74HC00 (Quad 2-input NAND) V DD = 5 V, C PD = 22 pF, C L = 50 pF P D = (22 pF + 50 pF) * (5 V) 2 * f T F T (Hz)P D 1K1.8  W 1M1.8 mW 100M180 mW I DDmax = 20  A P S = V DD * I DDmax = 5 V * 20  A = 100  W

21 ECE 331 - Digital System Design21 Power Dissipation Total Power Consumption

22 ECE 331 - Digital System Design22 Total Power Consumption P T = P S + P D Compare P T for Quad 2-input NAND (74xx00) 0 Hz1 MHz100 MHz TTL15.8 mW15.8 mW15.8 mW CMOS100  W1.805 mW180 mW Compare TTL and CMOS TTLCMOS P S V CC * I CC V DD * I DD P D ~ 0 W(C PD + C L ) * V 2 DD * f T

23 ECE 331 - Digital System Design23 Propagation Delay

24 ECE 331 - Digital System Design24 Definitions Propagation Delay: The time from a change in one input to the final change in the output Maximum Delay: Worst-case delay Typical Delay: Mean delay Minimum Delay: Fastest possible The specifications for maximum, typical, and minimum delay are those measured by the manufacturer for the given conditions

25 ECE 331 - Digital System Design25 Propagation Delay The time delay between a change in the input and the corresponding change in the output  t PHL = time for output to transition from high to low  t PLH = time for output to transition from low to high Ideal Propagation Delay input output t PHL t PLH

26 ECE 331 - Digital System Design26 Propagation Delay

27 ECE 331 - Digital System Design27 Propagation Delay Propagation delay is used to determine  When outputs are valid  The maximum speed of a combinational circuit  The maximum frequency of a sequential circuit

28 ECE 331 - Digital System Design28 Simple Analysis Given: A logic circuit with multiple inputs and a single output. Given: A single transition on one of the inputs. Determine: The time delay to propagate the transition on the input to the output.  Use the propagation delay specified for each gate in the path between the input on which the transition occurred and the output.  The gate propagation delays are specified in the associate datasheets.

29 ECE 331 - Digital System Design29 More Complex Analysis Problem: Some circuits have more than one path from an input to an output. Solution:  Analyze every possible delay path or  Use the Worst Case Analysis Provides a conservative specification Often sufficient

30 ECE 331 - Digital System Design30 More Complex Analysis Problem: What if multiple inputs change at the same time? Solution:  Analyze all combinations of input changes for all delay paths (to the output). or  Use the Worst Case Analysis

31 ECE 331 - Digital System Design31 Sum of Worst Cases (SWC) Analysis Write worst case delay next to each logic gate  Select maximum of t PLH and t PHL Identify all input-output paths (i.e. all delay paths) Calculate worst case delay for each path  Summarize in table Select worst case (i.e. maximum propagation delay)

32 ECE 331 - Digital System Design32 Example: Determine the worst-case propagation delay using the SWC Analysis for the XOR Logic Circuit.

33 ECE 331 - Digital System Design33 Example f x 1 x 2 74LS04 74F04 74F08 74LS08 74F32 TPLHTPHL mintypmaxmintypmax 74LS04091501014 74F042.43.76.01.53.25.4 74LS08081801020 74F082.43.76.22.03.25.3 74F322.43.76.11.83.25.5

34 ECE 331 - Digital System Design34 Example f x 1 x 2 74LS04 74F04 74F08 74LS08 74F32 TPLHTPHL mintypmaxmintypmax 74LS04091501014 74F042.43.76.01.53.25.4 74LS08081801020 74F082.43.76.22.03.25.3 74F322.43.76.11.83.25.5 TP = 32.1

35 ECE 331 - Digital System Design35 Example f x 1 x 2 74LS04 74F04 74F08 74LS08 74F32 TPLHTPHL mintypmaxmintypmax 74LS04091501014 74F042.43.76.01.53.25.4 74LS08081801020 74F082.43.76.22.03.25.3 74F322.43.76.11.83.25.5 TP = 12.3

36 ECE 331 - Digital System Design36 Example f x 1 x 2 74LS04 74F04 74F08 74LS08 74F32 TPLHTPHL mintypmaxmintypmax 74LS04091501014 74F042.43.76.01.53.25.4 74LS08081801020 74F082.43.76.22.03.25.3 74F322.43.76.11.83.25.5 TP = 26.1

37 ECE 331 - Digital System Design37 Example f x 1 x 2 74LS04 74F04 74F08 74LS08 74F32 TPLHTPHL mintypmaxmintypmax 74LS04091501014 74F042.43.76.01.53.25.4 74LS08081801020 74F082.43.76.22.03.25.3 74F322.43.76.11.83.25.5 TP = 27.3

38 ECE 331 - Digital System Design38 Example InputOutputDelay X1F32.1 X1F12.3 X2F26.1 X2F27.3 Worst Case Propagation Delay = 32.1

39 ECE 331 - Digital System Design39 SWC Analysis - Summary Permits Worst Case assessment of delay Simple / Robust Conservative  If it does not satisfy the design requirements it may be necessary to implement a more detailed analysis.  In particular, with the case-limiting paths

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