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ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002.

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Presentation on theme: "ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002."— Presentation transcript:

1 ECE C03 Lecture 71 Lecture 7 Delays and Timing in Multilevel Logic Synthesis Hai Zhou ECE 303 Advanced Digital Design Spring 2002

2 ECE C03 Lecture 72 Outline Gate delays Timing waveforms Performance calculations Static/dynamic hazards and glitches Designs to avoid hazards READING: Katz 3.3, 3.4, 3.5.2, Dewey 6.5.1, 6.5.2

3 ECE C03 Lecture 73 Time Response in Combinational Networks emphasis on timing behavior of circuits waveforms to visualize what is happening simulation to create these waveforms momentary change of signals at the outputs: hazards can be useful— pulse shaping circuits can be a problem — glitches: incorrect circuit operation Terms: gate delay— time for change at input to cause change at output minimum delay vs. typical/nominal delay vs. maximum delay careful designers design for the worst case! rise time— time for output to transition from low to high voltage fall time— time for output to transition from high to low voltage

4 ECE C03 Lecture 74 Concepts of Delays and Timing For a given gate, the gate delay refers to the time it takes the output signal to respond to in input transition input output

5 ECE C03 Lecture 75 Gate Delays Why is there a gate delay? There are actual resistances and capacitances inside digital logic If you apply a unit step voltage signal to an input, the output will not respond immediately, but after a delay proportional to R.C Input Output Capacitance of load Resistance of driver T delay = R.C

6 ECE C03 Lecture 76 Delays in Combinational Logic Input transition Output transition QUESTION: After the input goes from low to high how long does it take for the output to go from low to high (note depends on other inputs being 1 or 0) ANSWER: Use simple delay models for each gate and add up delays in a path from input to output

7 ECE C03 Lecture 77 Delays in Combinational Logic Wire load Capacitance C Load capacitance (pF) Delay (nsec) Low drive High drive

8 ECE C03 Lecture 78 Designing Logic With High Performance Input transition QUESTION: Suppose the delay from input to output is 30 nsec and is unacceptable. How would you make a higher performance design? ANSWER: Reduce capacitances at various loads, or use higher drive gates Reduce high load due to fanout Higher drive gate

9 ECE C03 Lecture 79 Gate Delays for Typical TTL Families Delays in nano-seconds

10 ECE C03 Lecture 710 Example gate delays in nanoseconds for LSI Logic 1.5 micron gate array 2 input AND gate. tpLH = Propagation delay from low to high transition at output tpHL = Propagation delay from high to low transition at output Gate Delay Specifications

11 ECE C03 Lecture 711 Pulse Shaping Circuit F is not always 0, pulse width equals 3 gate delays D remains high for three gate delays after A changes from low to high 100 A B C D F AB C D F

12 ECE C03 Lecture 712 Another Pulse Shaping Circuit Initially undefined Close Switch Open Switch + AB CD Open Switch Resistor ABCDABCD

13 ECE C03 Lecture 713 Hazards and Glitches Unwanted switching at the outputs Occur because delay paths through the circuit experience different propagation delays Danger if logic "makes a decision" while output is unstable OR hazard output controls an asynchronous input (these respond immediately to changes rather than waiting for a synchronizing signal called a clock) Usual solutions: wait until signals are stable (by using a clock) never, never, never use circuits with asynchronous inputs design hazard-free circuits Suggest that first two approaches be used, but we'll tell you about hazard-free design anyway!

14 ECE C03 Lecture 714 Kinds of Hazards Input change causes output to go from 1 to 0 to 1 Input change causes output to go from 0 to 1 to 0 Input change causes a double change from 0 to 1 to 0 to 1 OR from 1 to 0 to 1 to 0 Static 0-hazard Dynamic hazards Static 1-hazard

15 ECE C03 Lecture 715 Example of a Glitch F = A' D + A C' input change within product term input change that spans product terms output changes from 1 to 0 to 1 G1 G2 G3 A \C \A D F G1 G2 G3 A \C \A D F ABCD = 1100 ABCD = 1101 G1 G2 G3 A \C \A D F G1 G2 G3 A \C \A D F ABCD = 1101 ABCD = 0101 (A is still 0) G1 G2 G3 A \C \A D F ABCD = 0101 (A is 1) A AB C CD D B

16 ECE C03 Lecture 716 Eliminating Glitches General Strategy: add redundant terms F = A' D + A C' becomes A' D + A C' + C' D This eliminates 1-hazard? How about 0-hazard? Express F in PoS form: F = (A' + C')(A + D) Glitch present! Add term: (C' + D) A AB C CD D B

17 ECE C03 Lecture 717 How to design Circuits without Glitches Theorem: Under the assumption of one input switching, 2-level SOP has no 0-hazard and POS has no 1-hazard. Avoid 1-hazard in SOP: all adjacent 1’s are covered by same products F = A C' + A' D + C' D Avoid 0-hazard in POS: all adjacent 0’s are covered by same sums F = (A’+C’)(A+D)(C’+D)

18 ECE C03 Lecture 718 Dynamic Hazards Example with Dynamic Hazard Three different paths from B or B' to output ABC = 000, F = 1 to ABC = 010, F = 0 different delays along the paths: G1 slow, G4 very slow Handling dynamic hazards very complex Beyond our scope G1 G2 G3 G5 G4 \A B \B \C F A Slow Very slow

19 ECE C03 Lecture 719 Summary Gate delays Timing waveforms Performance calculations Static/dynamic hazards and glitches Designs to avoid hazards NEXT LECTURE: Latches and Flip-flops READING: Katz 6


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