Download presentation

Presentation is loading. Please wait.

Published byCorey Page Modified over 3 years ago

1
Chapter 6 –Selected Design Topics Part 2 – Propagation Delay and Timing Logic and Computer Design Fundamentals

2
Overview Part 1 – The Design Space Part 2 – Propagation Delay and Timing Propagation Delay Delay Models Cost/Performance Tradeoffs Flip-Flop Timing Circuit & System Level Timing Part 3 – Asynchronous Interactions Part 4 - Programmable Implementation Technologies

3
6-2 Gate Propagation Delay Propagation delay is the time for a change on an input of a gate to propagate to the output. Delay is usually measured at the 50% point with respect to the H and L output voltage levels. High-to-low (t PHL ) and low-to-high (t PLH ) output signal changes may have different propagation delays. High-to-low (HL) and low-to-high (LH) transitions are defined with respect to the output, not the input. An HL input transition causes: an LH output transition if the gate inverts and an HL output transition if the gate does not invert.

4
Propagation Delay (continued) Propagation delays measured at the midpoint between the L and H values

5
Propagation Delay Example Find t PHL, t PLH and t pd for the signals given IN (volts) OUT (volts) t (ns) 1.0 ns per division

6
Delay Models Transport delay - a change in the output in response to a change on the inputs occurs after a fixed specified delay Inertial delay - similar to transport delay, except that if the input changes such that the output is to change twice in a time interval less than the rejection time, the output changes do not occur. Models typical electronic circuit behavior, namely, rejects narrow “pulses” on the outputs

7
Delay Model Example A A B: Transport Delay (TD) Inertial Delay (ID) B Time (ns)0426810121416 No Delay (ND) abcde Propagation Delay = 2.0 ns Rejection Time = 1.0 ns

8
Circuit Delay Suppose gates with delay n ns are represented for n = 0.2 ns, n = 0.4 ns, n = 0.5 ns, respectively: 0.2 0.5 0.4

9
Consider a simple 2-input multiplexer: With function: Y = B for S = 1 Y = A for S = 0 “Glitch” is due to delay of inverter A 0.4 0.5 0.4 S B Y 0.2 Circuit Delay A S B Y S

10
Fan-out and Delay The fan-out loading (a gate’s output) affects the gate’s propagation delay Example 6-1:( page 324) One realistic equation for t pd for a NAND gate with 4 inputs is: t pd = 0.07 + 0.021 × SL ns SL is the number of standard loads the gate is driving, i. e., its fan-out in standard loads 4-input NOR gate—0.8 standard load 3-input NAND gate—1.0 standard load Inverter—1.0 standard load For SL = 4.5, t pd = 0.165 ns, what is the maximum standard loads? If this effect is considered, the delay of a gate in a circuit takes on different values depending on the circuit load on its output.

11
t s - setup time t h - hold time t w - clock pulse width T p- - propa- gation delay t PHL - High-to- Low t PLH - Low-to- High t pd - max (t PHL, t PLH ) 6-3 Flip-Flop Timing

12
Flip-Flop Timing Parameters t s - setup time the time that inputs S and R or D must be maintained at a constant value prior to the occurrence of the clock transition Master-slave - Equal to the width of the triggering pulse Edge-triggered - Equal to a time interval that is generally much less than the width of the the triggering pulse

13
Flip-Flop Timing Parameters t h - hold time minimum time for which the inputs must not change after the clock transition that causes the output to change Often is set to zero t w -minimum clock pulse width to ensure that the master has time enough to capture the input values correctly T p- - propagation delay Same parameters as for gates except Measured from clock edge that triggers the output to the output change

14
6-4 Sequential Circuit Timing

15
New Timing Components t p - clock period - The interval between occurrences of a specific clock edge in a periodic clock t pd,COMB - total delay of combinational logic along the path from flip-flop output to flip- flop input t slack - extra time in the clock period in addition to the sum of the delays and setup time on a path Must be greater than or equal to zero on all paths for correct operation Circuit and System Level Timing

16
Timing components along a path from flip-flop to flip-flop Circuit and System Level Timing (a) Edge-triggered (positive edge) t p t pd,FF t pd,COMB t slack t s C (b) Pulse-triggered (negative pulse) t p t pd,FF t pd,COMB t slack t s C

17
Timing Equations t p = t slack + (t pd,FF + t pd,COMB + t s ) For t slack greater than or equal to zero, t p ≥ max (t pd,FF + t pd,COMB + t s ) for all paths from flip-flop output to flip-flop input Circuit and System Level Timing

18
Example 6-2 Suppose that all the flip-flops used are the same t pd =0.2 ns t s =0.1 ns t pd,COMB =1.3 ns t p =1.5 ns t slack =-0.1 ns t p is too small t p >= 1.6ns f max =625 MHz

Similar presentations

OK

1 Lecture 28 Timing Analysis. 2 Overview °Circuits do not respond instantaneously to input changes °Predictable delay in transferring inputs to outputs.

1 Lecture 28 Timing Analysis. 2 Overview °Circuits do not respond instantaneously to input changes °Predictable delay in transferring inputs to outputs.

© 2018 SlidePlayer.com Inc.

All rights reserved.

Ads by Google

Ppt on nature and human health Maths ppt on statistics for class 9 Ppt on charge coupled device ppt Ppt on famous indian entrepreneurship Download ppt on mind controlled robotic arms for people Ppt on solid dielectrics wiki Ppt on power sharing in democracy it is important Ppt on different solid figures and nets Ppt on indian construction industry Ppt on bill gates leadership