1. Lecture #41: Active devices
This week we will be reviewing the material learned during the course
Today: review
Active circuits
Digital logic
CMOS transistors
12/8/2004
EE 42 fall 2004 lecture 41

2. Example of the Load-Line Method
Lets hook our 2K resistor + 2V source circuit up to an LED (light-emitting diode), which is a very nonlinear element with the IV graph shown below.
Again we draw the I-V graph of the 2V/2K circuit on the same axes as the graph of the LED. Note that we have to get the sign of the voltage and current correct!!
At the point where the two graphs intersect, the voltages and the currents are equal, in other words we have the solution. I 2 4
(ma)
V (Volt) 5 I + - V
Solution: I = 0.7mA, V = 1.4V
LED + - 2V 2K
LED
12/8/2004
EE 42 fall 2004 lecture 41

3. Simplification for time behavior of RC Circuits
Before any input change occurs we have a dc circuit problem (that is we can use dc circuit analysis to relate the output to the input).
Long after the input change occurs things “settle down” …. Nothing is changing …. So again we have a dc circuit problem.
time
voltage
input
We call the time period during which the output changes the transient
time
voltage
output
We can predict a lot about the transient behavior from the pre- and post-transient dc solutions
12/8/2004
EE 42 fall 2004 lecture 41

4. RC RESPONSE + Vout - Input node Output node ground R C
Example – Capacitor uncharged: Apply voltage step of 5 V
time
Vin 5
Vout
Input node
Output node
ground R C
Vin
Vout + -
Clearly Vout starts out at 0V ( at t = 0+) and approaches 5V.
We know this because of the pre-transient dc solution (V=0) and post-transient dc solution (V=5V).
So we know a lot about Vout during the transient - namely its initial value, its final value , and we know the general shape .
12/8/2004
EE 42 fall 2004 lecture 41

5. Actual exponential voltage versus time.
LOGIC GATE DELAY D
Time delay D occurs between input and output: “computation” is not instantaneous
Value of input at t = 0+ determines value of output at later time t = D F A B
Capacitance to Ground
Logic State
Input (A and B tied together) 1 t
Output (Ideal delayed step-function) 1 D F
Actual exponential voltage versus time. t
12/8/2004
EE 42 fall 2004 lecture 41

6. SIGNAL DELAY: TIMING DIAGRAMS
Show transitions of variables vs time
Oscilloscope Probe A B C D
Logic state 1 A t
Note B changes one gate delay after A switches B t t
Note that C changes two gate delays after A switches. C t t 2t
Note that D changes three gate delays after A switches. t 2t 3t D
12/8/2004
EE 42 fall 2004 lecture 41

7. EXAMPLE OF THE USE OF DEPENDENT SOURCE IN THE MODEL FOR AN AMPLIFIER
V0 depends only on input (V+  V-) +  A V+ V V0
Differential Amplifier
AMPLIFIER SYMBOL +  V0
AV1 V1 Ri
Circuit Model in linear region
AMPLIFIER MODEL
See the utility of this: this Model when used correctly mimics the behavior of an amplifier but omits the complication of the many many transistors and other components.
12/8/2004
EE 42 fall 2004 lecture 41

8. NODAL ANALYSIS WITH DEPENDENT SOURCES
Example circuit: Voltage controlled voltage source in a branch R5 R 4
VAA + 
ISS 3 1 V a b A v c 6 2
Write down node equations for nodes a, b, and c.
(Note that the voltage at the bottom of R2 is “known” so current flowing down from node a is (Va  AvVc)/R2.)
CONCLUSION:
Standard nodal analysis works
12/8/2004
EE 42 fall 2004 lecture 41

9. NODAL ANALYSIS WITH DEPENDENT SOURCES
Finding Thévenin Equivalent Circuits with Dependent Sources Present
Method 1: Use Voc and Isc as usual to find VT and RT (and IN as well)
Method 2: To find RT by the “ohmmeter method” turn off only the independent sources; let the dependent sources just do their thing.
12/8/2004
EE 42 fall 2004 lecture 41

10. NODAL ANALYSIS WITH DEPENDENT SOURCES
Example : Find Thévenin equivalent of stuff in red box. V R V a 3 c R 2
ISS R + 6 A V  v cs
With method 2 we first find open circuit voltage (VT) and then we “measure” input resistance with source ISS turned off.
You verify the solution:
12/8/2004
EE 42 fall 2004 lecture 41

11. EXAMPLE: AMPLIFIER ANALYSIS
USING THE AMPLIFIER MODEL WITH Ri = infinity:
Assume the voltage between the inputs is zero, and then figure out if that is consistent, or if the amplifier will hit a rail. +  A V- V+ V0 RF RS
VIN + 
AV1 - V1 V- V+ V0 RF RS
VIN
Method: We substitute the amplifier model for the amplifier, and perform standard nodal analysis
solution: RIN = VO/VIN =
12/8/2004
EE 42 fall 2004 lecture 41

12. OP-AMPS AND COMPARATORS
A very high-gain differential amplifier can function either in extremely linear fashion as an operational amplifier (by using negative feedback) or as a very nonlinear device – a comparator. Let’s see how! +  A V+ V V0
Differential Amplifier +  V0
AV1 V1 Ri
Circuit Model in linear region
“Differential”  V0 depends only on difference (V+  V-)
“Very high gain” 
But if A ~ , is the output infinite?
The output cannot be larger than the supply voltages. It will limit or “clip” if we attempt to go too far. We call the limits of the output the “rails”.
12/8/2004
EE 42 fall 2004 lecture 41

13. WHAT ARE I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER ?
Circuit model gives the essential linear part
But V0 cannot rise above some physical voltage related to the positive power supply VCC (“ upper rail”) V0 < V+RAIL
And V0 cannot go below most negative power supply, VEE i.e., limited by lower “rail” V0 > V-RAIL +  V0
VIN
Example: Amplifier with gain of 105, with max V0 of 3V and min V0 of 3V.
VIN(V) 1 2 3
V0 (V)
0.1
0.2 3 2 1
.2
(a)
V-V near origin 3
(b)
V-V over wider range
VIN(V) 10 20 30
V0 (V) 1
30
20
10 2 1 2 3
upper “rail”
lower “rail”
12/8/2004
EE 42 fall 2004 lecture 41

14. THE RAILS
The output voltage of an amplifier is of course limited by whatever voltages are supplied (the “power supplies”). Sometimes we show them explicitly on the amplifier diagram, but often they are left off. +  A V+ V ) V ( -
V0=
Differential Amplifier +  A V+ V ) V ( -
V0=
VDD=2V
VSS=0
If the supplies are 2V and 0V, the output cannot swing beyond these values. (You should try this experiment in the lab.) For simplicity we will use the supply voltages as the rails.
So in this case we have upper rail = 2V, lower rail = 0V.
12/8/2004
EE 42 fall 2004 lecture 41

15. I-V CHARACTERISTICS OF AN ACTUAL HIGH-GAIN DIFFERENTIAL AMPLIFIER (cont.)
Example: Amplifier with gain of 105, with upper rail of 3V and lower rail of 3V. We plot the V0 vs VIN characteristics on two different scales
VIN(V) 1 2 3
V0 (V) 3 2 1
(c)
Same V0 vs VIN over even wider range 3
(b)
V-V over wide range
VIN(V) 10 20 30
V0 (V) 1
30
20
10 2 1 2 3
upper “rail”
lower “rail”
12/8/2004
EE 42 fall 2004 lecture 41

16. A A AND NAND C=A·B C = B B A A C = NOR C=A+B OR B B A A B NOT
Logic Gates
These are circuits that accomplish a given logic function such as “OR”. We will shortly see how such circuits are constructed. Each of the basic logic gates has a unique symbol, and there are several additional logic gates that are regarded as important enough to have their own symbol. The set is: AND, OR, NOT, NAND, NOR, and EXCLUSIVE OR. A B
C=A·B
AND A
NAND
C = B
NOR A B OR A B
C=A+B
C =
EXCLUSIVE OR A B
NOT A
12/8/2004
EE 42 fall 2004 lecture 41

17. Evaluation of Logical Expressions with “Truth Tables”
The Truth Table completely describes a logic expression
In fact, we will use the Truth Table as the fundamental meaning of a logic expression.
Two logic expressions are equal if their truth tables are the same
12/8/2004
EE 42 fall 2004 lecture 41

18. Defined from form of truth tables
Some Useful Theorems 1) 2) 3) 4) 6) 7) 8) 9)
Defined from form of truth tables
Communicative
Associative
Each of these can be proved by writing out truth tables
Distributive
} de Morgan’s Laws
12/8/2004
EE 42 fall 2004 lecture 41

19. Designing the combinatorial logic circuit, con’t
Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS. If we may use De Morgan’s theorem we may turn the sum-of-products expression into a form directly implementable entirely with NAND gates. (We also need the NOT function, but that is accomplished by a one-input NAND gate). function.
Starting with any SUM-OF-PRODUCTS expression:
Y = ABC+DEF we can rewrite it by “inverting” with De Morgan:
Clearly this expression is realized with three NAND gates: one three-input NAND for , one for , and one two-input gate to combine them: A B Y C D E F
The NAND realization, while based on DeMorgan’s theorem, is in fact much simpler: just look at the sum of products expression and use one NAND for each term and one to combine the terms.
12/8/2004
EE 42 fall 2004 lecture 41

20. Designing the combinatorial logic circuit, con’t
Synthesis
Designing the combinatorial logic circuit, con’t
Method 3: NAND GATE SYNTHESIS (CONTINUED).
Two Examples of SUM-OF-PRODUCTS expressions:
(X-OR function) A Y B C A X B
(No connection)
We could make the drawings simpler by just using a circle for the NOT function rather than showing a one-input NAND gate
12/8/2004
EE 42 fall 2004 lecture 41

21. Controlled Switch Model of Inverter
Input
Output RN - +
SP is closed if VIN < VDD by 2V RP
VDD = 3V
VSS = 0V SN SP
SN is closed if VIN > VSS by 2V
VIN
VOUT
Note top, type P, switch is “upside down”
The idea: If input is 3V then top switch open, bottom one closed. And if input is 0V, bottom switch is open, and top switch closed. Thus we connect the output (through one of the resistors RP or RN) to either ground or VDD.
12/8/2004
EE 42 fall 2004 lecture 41

22. CMOS Both NMOS and PMOS on a single silicon chip
NMOS needs a p-type substrate
PMOS needs an n-type substrate
But we can build in the same substrate by changing doping type G D D G S S
oxide p
n-well
p-well n n
We can butt the p and n together, or even let, for example the entire non n-well region be p type.
12/8/2004
EE 42 fall 2004 lecture 41

23. Basic CMOS Inverter OUT IN CMOS Inverter Inverter
p-ch
VDD
OUT IN
n-ch
CMOS Inverter
Inverter IN
OUT
VDD
Example layout of CMOS Inverter
12/8/2004
EE 42 fall 2004 lecture 41

24. Al “wires” VDD IN PMOS Gate N-WELL OUT NMOS Gate GROUND 12/8/2004
EE 42 fall 2004 lecture 41

25. NMOS Transistor VDS VGS ID IG + VGS IG _ ID - VDS + drain gate source
metal
metal
oxide insulator
metal
n-type
n-type
p-type
metal +
VGS _ G IG ID S D
- VDS +
12/8/2004
EE 42 fall 2004 lecture 41

26. NMOS I-V CharacteristicG +
VGS _ IG ID S D
- VDS +
Since the transistor is a 3-terminal device, there is no single I-V characteristic.
Note that because of the insulator, IG = 0 A.
We typically define the MOS I-V characteristic as
ID vs. VDS for a fixed VGS.
The I-V characteristic changes as VGS changes.
12/8/2004
EE 42 fall 2004 lecture 41

27. cutoff mode (when VGS < VTH(N))
NMOS I-V Curves ID
triode mode
saturation mode
VGS = 3 V
VDS = VGS - VTH(n)
VGS = 2 V
VGS = 1 V
VDS
cutoff mode (when VGS < VTH(N))
12/8/2004
EE 42 fall 2004 lecture 41

28. Saturation in a MOS transistor
At low Source to drain voltages, a MOS transistor looks like a resistor which is “turned on” by the gate voltage
If a more voltage is applied to the drain to pull more current through, the amount of current which flows stops increasing→ an effect called pinch-off.
Think of water being sucked through a flexible wall tube. Dropping the pressure at the end in order to try to get more water to come through just collapses the tube.
The current flow then just depends on the flow at the input: VGS
This is often the desired operating range for a MOS transistor (in a linear circuit), as it gives a current source at the drain as a function of the voltage from the gate to the source.
12/8/2004
EE 42 fall 2004 lecture 41