Presentation on theme: "CH14 BIPOLAR DIGITAL CIRCUITS The Ideal BJT Transistor Switch"— Presentation transcript:
1CH14 BIPOLAR DIGITAL CIRCUITS The Ideal BJT Transistor Switch The switch terminalsare the collector and emitter.The transistor switch is:OFF when VBE is zero or negative R ON when VBE is positive(These conditions are approximated with a practical transistor switch.)
2The Practical BJT Transistor Switch Transistor State:ON – Operating point Is in the Saturation RegionVCE = saturation value typically 0.2 voltsVCE = 0 for the ideal case(device is said to be operating in the saturation region when VCE is less than about 0.7 volts.)OFF – Operating point is in the cutoff region(the cutoff region exists below the level of IB = 0.)Note that when IB = 0, IC is not zero. Instead a small leakagecurrent called ICBO (or ICO) flows (typically1mA).VCE = VCC – ICBO x RLVCE = VCC for the ideal case
3Transistor Switching Times Because of internal capacitive effects, transistors do not switch in zero time.Time relationships between iC and vi for the simple inverter
4Transistor Switching Times Delay Time – t d – the time required for IC to reach 10% of its final level after IB has commenced. It is due to mainly the time needed to charge the EBJ depletion capacitance to the forward-bias voltage VBE.Rise Time – t r – the time it takes for IC to go from 10% to 90% of its maximum level. (Occurs after the delay time.)Turn-On Time – t on = t d + t rStorage Time – t s – the time between IB switch off and IC falling to 90% of its maximum level – due to the fact that the CBJ is FWD biased in saturation. – excess minority charge carriers, stored in the depletion region must be withdrawn or recombine before begins IC to fall.Fall Time – t f – the time it takes for IC to fall from 90% to 10% of its maximum.Turn-Off Time – t off = t s + t f
5Conceptual Circuit (Inverter) CH14 INTRODUCTION TO TTLConceptual Circuit (Inverter)Analysis for Case: Input = logic HI (e.g. 5volts)In this case Q1 operates in the inverse active mode with avery low bR 0.02Base-Collector junction of Q1 is forward biasedBase-Emitter junction of Q1 is reverse biased(see currents marked on Fig )Gate input current = bR I I – very smallQ3 base current = (bR + 1) I IR is chosen so that I is large enough to drive Q3 into saturation with LO output voltage 0.2 volts
6Conceptual Circuit (Inverter) CH14 INTRODUCTION TO TTLConceptual Circuit (Inverter) 5V+0.3VAnalysis for Case: Input = logic LO (e.g. 0.2 volts)In this case Q1 operates in the normal active mode with a bF large valueBase-Emitter junction of Q1 is forward biased and base voltage = = 0.9 voltsCollector current of Q1 = bF I (large value) which rapidly discharges the base of Q3 (initially still at 0.7 volts and saturated immediately after switching) rapidly driving it into cutoff with a reduced base voltage 0.3volts.This reduced base voltage is the collector voltage of Q1 so Q1 saturates with VCE sat 0.1v and negligibly small collector current. Its base voltage is then 0.3v the base voltage of Q3, keeping Q3 in cutoff and output level HI.
7Actual Complete Circuit TTL Gate (NAND) BASIC FEATURES: (Analysis for case of inverter done later)Input Stage based on Q1 – also known as multi-emitter input.(Protection diodes shown on actual circuit do not affect logic function.)Driver Stage based on Q2 – also known as phase-splitter.--Causes either Q3 or Q4 to turn on while other is off.Output Stage based on Q3 and Q4 -- also known astotem-pole output. – Provides active pull-up through Q3.
8Analysis when Input is HI Circled numbers in Fig. give order of analysis.(Our analysis relies on prior understanding gained from the conceptual circuit analysis already completed.)1. Q3 is on and has 0.7v at its base2. Q2 is on supplying Q3 with sufficient base current to drive it into saturation.3. Q1 is operating in the inverse active mode with BC junction FWD biased (0.7v), so its base voltage is = 2.1v4. Ohm’s law gives current through 4k resistor.5. Gate input current IIH = Q1’s inverse mode emitter current =bR I6. Q2’s base current = Q1’s inverse mode collector current= (bR +1) I 0.73mA7. Q2’s collector voltage = VBE3 + VCE sat = 0.9v8. Ohm’s law gives current in 1.6k resistor = 2.6 mA.9. The 0.9v at Q4’s base cannot turn it on due to diode D, so IB4 = 010. For Q2, IE = IC + IB = 3.3mA
9Analysis when Input is HI 11. Current through 1k resistor by Ohm’s law12. Current into base of Q3 by KCL13. Output voltage of gate is VCE SAT of Q3In the LO output state Q3 can sink a load currentI L <= b x 2.6mAIf this value is exceeded – no longer in saturation and outputlogic LO voltage level not maintained within specified limits.(Fig. shows Q3 leaving saturation at higher load current).There is thus a limit on allowable load current that is directlyrelated to the gate’s maximum fan-out.The Fig. is simply the vCE vs. iC characteristic curve of Q3at the base current it has when output is LO.
10Analysis when Input is LO 1. BE junction of Q1 is FWD biased and base voltage = 0.9v2. Ohm’s law gives current in 4k resistor.4. 0.9v is insufficient to FWD bias the series combination of CBjunction of Q1 and BE junction of Q2, so Q2 is cutoff and Q1 has zero collector current.3. For Q1, IE = IB + IC = IB + 0 = I 1mA.5. For Q1, VC = VCE SAT + VI = 0.3v6. For Q2 (cutoff), VE = IE x 1k = 07. Q3 is also cutoff with base current = 0 mA
11Analysis when Input is LO Q4 supplies the load current when input is LO (output HI)Gate output terminal open:v0 = 5 – (IB4 X 1.6k) – 0.65 – 0.65 5 – 0.65 – 0.65 = 3.7v (since IB4 0)Q4 supplying load current large enough to cause it to saturate:v0 = VCC – iL x 130 – VCE SAT4 – VDQ4 supplying load current below value causing saturation while in active mode:v0 = VCC – iL /(b +1) x 1.6k – VBE4 – VD
12Function of 130 Ohm Resistance Function is to limit the current through the pull-up transistor Q4.Limit current due to:Accidental short-circuit to ground.Current pulse due to Q3 and Q4 briefly on at thesame time during HI to LO transition.(Q3 needs extra time to turn off (discharging thebase through the 1k) after Q2 has causedQ4 to turn on.)TTL Supply BypassingThe current pulses due to the brief time when both outputtransistors of the totem pole turn on, are current spikeswhich cause corresponding voltage spikes superimposedon VCC that can be coupled to other components of the digital system.Thus bypassing capacitors should be connected betweenThe VCC rail and ground at frequent locations.(Usually at the VCC pins of the IC’s).Check IC manufacturer’s application notes forRecommended practice.