1. March 16-18, 2008SSST'20081 Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal Department of Electrical and Computer Engineering Auburn University, AL 36849 USA 40 th Southeastern Symposium on System Theory

2. March 16-18, 2008SSST'20082 Outline  Background  Problem Statement  Analysis  Results and Discussion  Conclusion

3. March 16-18, 2008SSST'20083 Motivation for This Work  With the continuous downscaling of CMOS technologies, the device reliability has become a major bottleneck.  The sensitivity of electronic systems can potentially become a major cause of soft (non-permanent) failures.  The determination of soft error rate in logic circuits is a complex problem.  It is necessary to analyze circuit reliability. However, there is no comprehensive work that considers all the factors that influence the soft error rate.

4. March 16-18, 2008SSST'20084 Strike Changes State of a Single Bit 01 Definition from NASA Thesaurus: “ Single Event Upset (SEU): Radiation-induced errors in microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs ”. “ Single Event Upset (SEU): Radiation-induced errors in microelectronic circuits caused when charged particles [also, high energy particles] (usually from the radiation belts or from cosmic rays) lose energy by ionizing the medium through which they pass, leaving behind a wake of electron-hole pairs ”.

5. March 16-18, 2008SSST'20085 Impact of Neutron Strike on a Silicon Transistor  Neutron is a major cause of electronic failures at ground level.  Another source of upsets: alpha particles from impurities in packaging materials. Strikes release electron & hole pairs that can be absorbed by source & drain to alter the state of the device + - + + + - - - Transistor Device source drain neutron strike

6. March 16-18, 2008SSST'20086 Cosmic Rays Earth’s Surface p n p p n n p p n n n  Neutron flux is dependent on altitude, longitude, solar activity etc. Source: Ziegler et al.

7. March 16-18, 2008SSST'20087 Problem Statement  Given background environment data  Neutron flux  Background energy (LET*) distribution *These two factors are location dependent.  Given circuit characteristics  Technology  Circuit netlist  Circuit node sensitive region data *These three factors depend on the circuit.  Estimate neutron caused soft error rate in standard FIT** units. *Linear Energy Transfer (LET) is a measure of the energy transferred to the device per unit length as an ionizing particle travels through material. Unit: MeV- cm 2 /mg. Failures In Time (FIT): Number of failures per 10 9 device hours **Failures In Time (FIT): Number of failures per 10 9 device hours

8. March 16-18, 2008SSST'20088 Measured Environmental Data  Typical ground-level neutron flux: 56.5cm -2 s -1.  J. F. Ziegler, “Terrestrial cosmic rays,” IBM Journal of Research and Development, vol. 40, no. 1, pp. 19.39, 1996.  Particle energy distribution at ground-level: “For both 0.5μm and 0.35μm CMOS technology at ground level, the largest population has an LET of 20 MeV-cm 2 /mg or less. Particles with energy greater than 30 MeV-cm 2 /mg are exceedingly rare.” “For both 0.5μm and 0.35μm CMOS technology at ground level, the largest population has an LET of 20 MeV-cm 2 /mg or less. Particles with energy greater than 30 MeV-cm 2 /mg are exceedingly rare.”  K. J. Hass and J. W. Ambles, “Single Event Transients in Deep Submicron CMOS,” Proc. 42 nd Midwest Symposium on Circuits and Systems, vol. 1, 1999. Linear energy transfer (LET), MeV-cm 2 /mg Probability density 0 15 30

9. March 16-18, 2008SSST'20089 Proposed Soft Error Model Occurrence rate

10. March 16-18, 2008SSST'200810 Pulse Widths Probability Density Propagation 1 X Y We use a “3-interval piecewise linear” propagation model 1) Non-propagation, if D in ≤τ p. 2) Propagation with attenuation, ifτ p < D in < 2τ p. 3) Propagation with no attenuation, if D in  2τ p. Where  D in : input pulse width  D out : output pulse width  τ p : gate input output delay τpτp 2τp2τp 0D in D out f X (x) f Y (y) Delay τ p

11. March 16-18, 2008SSST'200811 Validating Propagation Model Using HSPICE Simulation  Simulation of a CMOS inverter in TSMC035 technology with load capacitance 10fF

12. March 16-18, 2008SSST'200812 Pulse Width Density Propagation Through a CMOS Inverter

13. March 16-18, 2008SSST'200813 Soft Error Occurrence Rate Calculation for Generic Gate

14. March 16-18, 2008SSST'200814 SER Results on Workstation Sun Fire 280R Circuit#PIs#POs#Gates CPU s FIT/gate /output C175260.010.3679 C4323671600.041.0563 C49941322020.140.2188 C88060263830.080.3882 C190833258801.140.7427 C267023314011930.770.2882 C531517812323072.780.5572 C7552207108351210.820.6652

15. March 16-18, 2008SSST'200815 SER Results for Inverter Chains Circuit#PIs#POs #Gate s CUP (s) FIT/gate Inv21120.000.2819 Inv51150.000.5388 Inv1011100.000.9654 Inv2011200.00 1. 8185 Inv5011500.004.3780 Inv100111000.048.6473

16. March 16-18, 2008SSST'200816 Result Comparison Measured Data Logic Circuit SER Estimation Ground Level Ground Level Devices SER* SER*(FIT/Mbit) Our Work Our Work Rao et al. [1] 0.13µ SRAMs [2] 0.13µ SRAMs [2] 10,000 to 100,000 1,000 to 10,000 1x10 -5 to 8x10 -5 SRAMs, 0.25μ and below [3] 10,000 to 100,000 1 Gbit memory in 0.25µ [4] 4,200  The altitude is not mentioned for these data.  [1] R. R. Rao, K. Chopra, D. Blaauw, and D. Sylvester, “An Efficient Static Algorithm for Computing the Soft Error Rates of Combinational Circuits," Proceedings of the conference on Design automation and test in Europe, pp. 164-169, 2006.

17. March 16-18, 2008SSST'200817 Conclusion  SER in logic and memory chips will continue to increase as devices become more sensitive to soft errors at sea level.  By modeling the soft errors by two parameters, the occurrence rate and single event transient pulse width density, we are able to effectively account for the electrical masking of circuit.  Our approach considers more factors and thus gives more realistic soft error rate estimation.

18. March 16-18, 2008SSST'200818 References [2] J. Graham, “Soft errors a problem as SRAM geometries shrink,“http://www.ebnews.com/story/OEG200201 28S0079, ebn, 28 Jan 2002. [3] Wingyu Leung; Fu-Chieh Hsu; Jones, M. E., "The ideal SoC memory: 1T-SRAM TM," Proc.13th Annual IEEE International on ASIC/SOC Conference, pp. 32-36, 2000 [4] Report, “Soft Errors in Electronic Memory-A White Paper," Technical report, Tezzaron Semiconductor, 2004.