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Single Event Upsets (SEUs) – Soft Errors By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College.

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Presentation on theme: "Single Event Upsets (SEUs) – Soft Errors By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College."— Presentation transcript:

1 Single Event Upsets (SEUs) – Soft Errors By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX 1

2 Background pn junction behavior pn junction behavior Electric field Electric field Depletion region Depletion region Energy band diagram of Si Energy band diagram of Si Energy transferred to Si may excite an electron from valence band to conduction band Energy transferred to Si may excite an electron from valence band to conduction band e-h pairs can be generated e-h pairs can be generated 2

3 n+n+ S n+n+ p-substrate G D VDD Depletion Region Radiation Particle _ + + _ _ + _ + _ + _ + _ + E _ + VDD - V jn E Charge Deposition by a Radiation Particle – Drift and Diffusion Radiation particles - protons, neutrons, alpha particles and heavy ions Radiation particles - protons, neutrons, alpha particles and heavy ions Reverse biased p-n junctions are most sensitive to particle strikes Reverse biased p-n junctions are most sensitive to particle strikes Charge is collected at the drain node through drift and diffusion Charge is collected at the drain node through drift and diffusion Results in a voltage glitch at the drain node Results in a voltage glitch at the drain node System state may change if this voltage glitch is captured by at least one memory element System state may change if this voltage glitch is captured by at least one memory element This is called SEU This is called SEU May cause system failure May cause system failure B 3

4 4 Charge Deposited by a Radiation Particle Linear Energy Transfer (LET) is a common measure of the energy transferred by a radiation particle when it strikes a material Relationship between Q, LET and t Charge of 1 electron Therefore the charge deposited by a unit LET (for a track length of 1µm) So the charge deposited by a radiation strike (in terms of LET and track length) is

5 Other Charge Collection Mechanisms Bipolar Effect Bipolar Effect Parasitic bipolar transistor exists in MOSFETs Parasitic bipolar transistor exists in MOSFETs For example, n-p-n (S–B–D) in an NMOS transistor For example, n-p-n (S–B–D) in an NMOS transistor Holes accumulation in an NMOS transistor may turn on this bipolar transistor Holes accumulation in an NMOS transistor may turn on this bipolar transistor Alpha-particle Source-drain Penetration (ALPEN) Alpha-particle Source-drain Penetration (ALPEN) A radiation particle penetrates through both source and drain diffusions A radiation particle penetrates through both source and drain diffusions 5

6 Modeling a Radiation Particle Strike A radiation particle strike is modeled by a current pulse as A radiation particle strike is modeled by a current pulse as where:   is the collection time constant where:   is the collection time constant   is the ion track establishment constant   is the ion track establishment constant The radiation induced current always flows from n -diffusion to p -diffusion The radiation induced current always flows from n -diffusion to p -diffusion For an accurate analysis, device level simulation should be performed For an accurate analysis, device level simulation should be performed 6

7 Single Event Upsets Single Event Upsets (SEUs) or Soft Errors Single Event Upsets (SEUs) or Soft Errors Troublesome for both memories and combinational logic Troublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial designs Becoming increasingly problematic even for terrestrial designs A particle strike at the output of a combinational gate results in a Single Event Transient (SET) A particle strike at the output of a combinational gate results in a Single Event Transient (SET) If a memory latches wrong value -> SEU If a memory latches wrong value -> SEU A particle strike in a memory element may directly lead to an SEU event A particle strike in a memory element may directly lead to an SEU event 7

8 Radiation Hardening Approaches Can be classified into three categories Can be classified into three categories Device level Device level Circuit level Circuit level System level System level Device level – Fault avoidance Device level – Fault avoidance SOI devices are inherently less susceptible to radiation strikes SOI devices are inherently less susceptible to radiation strikes Low collection volumes Low collection volumes Still needs other hardening techniques to achieve SEU tolerance Still needs other hardening techniques to achieve SEU tolerance Bipolar effect significantly increases the amount of charge collected at the drain node Bipolar effect significantly increases the amount of charge collected at the drain node 8

9 System Level Radiation Hardening Approaches Fault detection and fault correction approaches Fault detection and fault correction approaches SEU events are detected using built in current sensors (BICS) (Gill et al.) SEU events are detected using built in current sensors (BICS) (Gill et al.) Error correction codes (Gambles et al.) Error correction codes (Gambles et al.) Triple modulo redundancy based approaches (Neumann et. al) Triple modulo redundancy based approaches (Neumann et. al) Classical way of radiation hardening Classical way of radiation hardening Area and power overheads are ~200% !!!! Area and power overheads are ~200% !!!! 9

10 Circuit Level Hardening Fault avoidance approach Fault avoidance approach Gate sizing is done to improve the radiation tolerance of a design (Zhou et al.) Gate sizing is done to improve the radiation tolerance of a design (Zhou et al.) Radiation tolerance improves Radiation tolerance improves Higher drive capability Higher drive capability Higher node capacitance Higher node capacitance Area, delay and power overheads can be large Area, delay and power overheads can be large Selectively harden critical gates Selectively harden critical gates 10

11 11 Diode Clamping based Hardening Approach Approach A - PN Junction Diode based SEU Clamping Circuits Approach A - PN Junction Diode based SEU Clamping Circuits G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Higher V T device Radiation Strike V (out) time V (outP) time Shadow Gate

12 12 Our Radiation Hardening Approach Approach B - Diode-connected Device based SEU Clamping Circuits Approach B - Diode-connected Device based SEU Clamping Circuits G GP in 1V 0V 1.4V -0.4V outP out D2 D1 Higher V T device Radiation Strike V (out) time V (outP) time I ds Performance of approach A is slightly better than B but with a higher area penalty than B. Therefore, we selected approach B Performance of approach A is slightly better than B but with a higher area penalty than B. Therefore, we selected approach B

13 13 Protection Performance - Example Circuit simulation is performed in SPICE Circuit simulation is performed in SPICE 65nm BPTM model card is used 65nm BPTM model card is used V DD = 1V V DD = 1V V T N = | V T P | = 0.22V V T N = | V T P | = 0.22V Radiation strike at output of 2X INV Radiation strike at output of 2X INV Q = 24 fC Q = 24 fC    145ps    145ps    45ps    45ps Approach B is used Approach B is used

14 Our Split-output Approach Phase 1 Phase 1 Gate level hardening Gate level hardening Phase 2 Phase 2 Block level hardening Block level hardening Selectively harden critical gates in a circuit Selectively harden critical gates in a circuit To keep area and delay overheads low To keep area and delay overheads low Reduce SER by 10X Reduce SER by 10X 14

15 Gate Level Hardening Approach in out2 out1 Radiation Particle out2 out1n inn inp out1p inp & inn out1n out1p out2 |V TP | VDD - V TN Static Leakage Paths A radiation particle strike at a reverse biased p-n junction results in a current flow from n-type diffusion to p-type diffusion A radiation particle strike at a reverse biased p-n junction results in a current flow from n-type diffusion to p-type diffusion A gate constructed using only PMOS (NMOS) transistors cannot experience 1 to 0 (0 to 1) upset A gate constructed using only PMOS (NMOS) transistors cannot experience 1 to 0 (0 to 1) upset INV1 INV2 INV1 15

16 Our Gate Level Hardening Approach out1n inn out1p out2 out1n inn out1p out2 inp X X inp & inn out1n out1p out2 |V TP | VDD - V TN Low V T transistors Radiation Tolerant Inverter Leakage currents are lower by ~100X Modified Inverter inp 16

17 Radiation Tolerant Inverter out1n inn out1p out2 inp inp & inn out1n out1p out2 X Radiation Particle Strike M1 M2 M3 M4 M5 M6 M7 M8 The voltage at out2 is unaffected X A radiation particle strike at any node of the first inverter (radiation tolerant inverter) does not affect the voltage at out2 Radiation Particle Strike X X X X 17

18 Radiation Tolerant Inverter Radiation particle strike at the outputs of INV1 Radiation particle strike at the outputs of INV1 Implemented using 65nm PTM with VDD=1V Implemented using 65nm PTM with VDD=1V Radiation strike: Q =150fC,   =150ps &   =38ps Radiation strike: Q =150fC,   =150ps &   =38ps out1n inn out1p inp out2 INV1 18

19 Block Level Radiation Hardening 100% SEU tolerance can be achieved by hardening all gates in a circuit but this will be very costly 100% SEU tolerance can be achieved by hardening all gates in a circuit but this will be very costly Protect only sensitive gates in a circuit to achieve good SEU tolerance or coverage Protect only sensitive gates in a circuit to achieve good SEU tolerance or coverage We obtain these sensitive gates using Logical Masking We obtain these sensitive gates using Logical Masking P LM (G) is the probability that the voltage glitch due to a radiation particle strike gets logically masked P LM (G) is the probability that the voltage glitch due to a radiation particle strike gets logically masked P Sen (G) = 1 – P LM (G) P Sen (G) = 1 – P LM (G) If we want to protect only 2 gates then we should to protect Gates 1 and 3 to maximize SEU tolerance If we want to protect only 2 gates then we should to protect Gates 1 and 3 to maximize SEU tolerance Gate 3 is the most sensitive Gate 3 is the most sensitive → Radiation Particle 0 P 1 = 0.25 P 0 = 0.75 P 1 = 0.5 P 0 = 0.5 For all inputs P 1 = 0.5 P 0 = 0.5 Gate P LM P Sen

20 Block Level Radiation Hardening Obtained P Sen for all gates in a circuit using a fault simulator Obtained P Sen for all gates in a circuit using a fault simulator Sort these gates in decreasing order of their P Sen Sort these gates in decreasing order of their P Sen Harden gates until the required coverage is achieved Harden gates until the required coverage is achieved Coverage is a good estimate for SER reduction (Zhou et al.) Coverage is a good estimate for SER reduction (Zhou et al.) Gates at the primary output of a circuit need to be hardened since P Sen = 1 for these gates Gates at the primary output of a circuit need to be hardened since P Sen = 1 for these gates The dual outputs of the hardened gates at the primary outputs drive the dual inputs of an SEU tolerant flip-flip (such as the flip-flop proposed by Liu et al.) The dual outputs of the hardened gates at the primary outputs drive the dual inputs of an SEU tolerant flip-flip (such as the flip-flop proposed by Liu et al.) 20

21 Critical Charge (Q cri ) Minimum amount of charge which can result in an SEU event Minimum amount of charge which can result in an SEU event Our hardened gates can tolerate a large amount of charge dumped by a radiation particle Our hardened gates can tolerate a large amount of charge dumped by a radiation particle Operating frequency of circuit determines Qcri Operating frequency of circuit determines Qcri Q cri is the amount of charge which results in a voltage glitch of pulse width T Q cri is the amount of charge which results in a voltage glitch of pulse width T in out1n out1p out2 CLK t1t1 T + t 1 2T + t 1 21

22 Experimental Results We implemented a standard cell library L using a 65nm PTM model card with VDD = 1.0V We implemented a standard cell library L using a 65nm PTM model card with VDD = 1.0V Implemented both regular and hardened versions of all cell types Implemented both regular and hardened versions of all cell types Applied our approach to several ISCAS and MCNC benchmark circuits Applied our approach to several ISCAS and MCNC benchmark circuits We implemented We implemented A tool in SIS to find the sensitive gates in a circuit A tool in SIS to find the sensitive gates in a circuit An STA tool to evaluate the delay of a hardened circuit obtained using our approach An STA tool to evaluate the delay of a hardened circuit obtained using our approach Layouts were created for all gates in our library for both regular and hardened versions Layouts were created for all gates in our library for both regular and hardened versions 22

23 Experimental Results Our SEU immune gates can tolerate high energy radiation particle strikes Our SEU immune gates can tolerate high energy radiation particle strikes Critical charge is extremely high (>520fC) for all benchmark circuits Critical charge is extremely high (>520fC) for all benchmark circuits Suitable for space and military application because of the presence of large number of high energy radiation particles Suitable for space and military application because of the presence of large number of high energy radiation particles Avg. Results Coverage % Area Ovh % Delay Ovh Area Mapped 90% % Delay Mapped 90% % Average results over several benchmark circuits mapped for area and delay optimality Average results over several benchmark circuits mapped for area and delay optimality 23

24 Comparison Our Hardening Approach Our approach is suitable for radiation environments with high energy particles Our approach is suitable for radiation environments with high energy particles Zhou et al. Our Approach 90% Coverage Area Ovh. 90%58% Delay Ovh. 8%28% Critical Charge ~150fC>520fC 24

25 SRAM Hardening Decrease recovery time Decrease recovery time Slow down feedback path Slow down feedback path Insert resistors in the feedback paths Insert resistors in the feedback paths Resistor Resistor Polysilicon Polysilicon Gated Gated Increases write delay Increases write delay 25

26 Conclusions SEUs are troublesome for both memories and combinational logic SEUs are troublesome for both memories and combinational logic Becoming increasingly problematic even for terrestrial designs Becoming increasingly problematic even for terrestrial designs Applications demand reliable systems Applications demand reliable systems Need to efficiently design radiation hardening approaches for both combinational and sequential elements Need to efficiently design radiation hardening approaches for both combinational and sequential elements Also need efficient analysis techniques to estimate SER of complex circuits Also need efficient analysis techniques to estimate SER of complex circuits SEU susceptibility can be checked during design phase SEU susceptibility can be checked during design phase Reduce the number of design iterations Reduce the number of design iterations 26

27 THANK YOU 27


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