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Single Event Upsets in Digital VLSI Circuits EYES Summer Internship Program 2007 University of New Mexico Vinay Jain Dr. Payman Zarkesh-Ha Final Year Undergraduate.

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Presentation on theme: "Single Event Upsets in Digital VLSI Circuits EYES Summer Internship Program 2007 University of New Mexico Vinay Jain Dr. Payman Zarkesh-Ha Final Year Undergraduate."— Presentation transcript:

1 Single Event Upsets in Digital VLSI Circuits EYES Summer Internship Program 2007 University of New Mexico Vinay Jain Dr. Payman Zarkesh-Ha Final Year Undergraduate Assistant Professor ECE Indian Institute of Technology Kanpur University of New Mexico

2 Acknowledgements

3 Outline  Introduction  Soft-Spot Analysis  Inverter Model proposed  Simulation Results  Extension of the Model

4 Introduction  Origin  Soft errors, Single Event Transients (SET) and Single Event Upsets (SEU)  Techniques to reduce SET propagation  Softness of a node Particle Strike in CMOS Digital VLSI circuits. SET and SEU Origin of Soft errors: cosmic neutrons and α- particles

5 Soft-Spot Analysis  Timing Masking Factor, T N Tendency of a node to allow noise in particular time window Computed using time delays and sensitive window durations of various gates in the path  Logic Masking Factor, L N Likelihood for noise at a node to logically reach the storage element Computed using probability of nodes in the path to acquire certain states  Electrical Masking Factor, E N Ability of a node to allow noise propagation with enough strength Computed from the characteristics of Noise Rejection Curves  Overall Softness, S N S N = T N *L N *E N

6 Noise Rejection Curves Noise Rejection Curves for an inverter and its effects as Load and Size of the inverter is varied

7 Inverter Model Proposed Model proposed is- replacement of MOS transistors with constant current sources the DC value of which is the average drain currents of the transistors

8 A. Velocity Saturation Effects in short channel MOSFETs υ = μ.E / (1 + E / E C ), E < E C = υ SAT, E > E C where E C = 2 υ SAT / μ V DSATn = V GTn / (1 + V GTn / E Cn. L n ) for short channel (small L n ) saturates to V DSATn = E Cn. L n as V GTn is increased = V GTn, long channel (large L n )

9 I DSATn = υ SATn.C ox.W n.( V GTn -V DSATn ) = υ SATn.C ox.W n.(V GTn ) 2 / (V GTn + E Cn. L n ) ~ υ SATn. C ox.W n.(V GTn ) for small channel MOSFETs (small L n ) ~ υ SATn. C ox.W n.(V GTn ) 2 / E Cn. L n for long channel MOSFETs (large L n )

10 B. Voltage Transfer Characteristic Voltage Transfer Characteristic for an Inverter (INVx1) Noise can propagate only when input pulse has magnitude greater than V m

11 C. Average Current Model I D V DS characteristic for an inverter (INVx1) for gate Voltage greater than V m I N =(I Dn ) avg = I DSATn (1 + λ n (V DD + V m )/ 2) I N = C n *. I DSATn where C n * = 1 + λ n (V DD + V m )/ 2

12 I P = (I Dp ) avg = [ (I P1 /2). + {(I P1 +I P2 )/2}.(V DD – V m – ) ] / (V DD – V m ) = I DSATp.(1 + λ p (V DD - V m )/ 2 – /(2.(V DD - V m )) ) Thus, I P = C p *. I DSATp where C p * = 1 + λ p (V DD - V m )/ 2 – /(2.(V DD - V m )) = V DSATp at V G = (V DD + V m )/ 2 I P1 = I DSATp. (1+λ p. ) I P2 = I DSATp. (1+λ p.(V DD - V m ))

13 Thus, we have I N = C n *I DSATn & I P = C p *I DSATp where both C n * & C p * are constants and close to unity. We can now calculate T C as the minimum duration required for a noise pulse of height V C volts, to propagate through the inverter as T C = C L.(V DD - V m )/(I N - I P ) with V G = V C The above equation gives a relation between T C and V C as a function of only Gate size (W and L) of p-MOS and n-MOS.

14 Simulation Results Noise Rejection Curves comparison for INVx2 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 4.45 sec Mean %error = 4.68% Noise Rejection Curves comparison for INVx1 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 4.48 sec Mean %error = 11.59%

15 Noise Rejection Curves comparison for INVx8 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 4.42 sec Mean %error = 17.65% Noise Rejection Curves comparison for INVx4 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 4.61 sec Mean %error = 6.70%

16 Extension of the model Modeling of NAND gates for easy computation of Noise Rejection Curves

17 Modeling of NOR gates for easy computation of Noise Rejection Curves

18 Noise Rejection Curves comparison for NANDx1 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 5.05 sec Mean %error = 30.16% Noise Rejection Curves comparison for NORx1 (Load = 200fF) Time taken for simulation by matlab = sec Time taken for simulation by Tspice = 5.09 sec Mean %error = 9.23%

19 References [1]C. Zhao, X. Bai, S. Dey, “A scalable soft spot analysis methodology for compound noise effects in nano-meter circuits,” DAC’04, pp , June [2]C. Zhao, S. Dey, “Improving transient error tolerance of digital VLSI circuits using RObustness COmpiler (ROCO),” International Symposium on Quality Electronic Design, ISQED’06 [3]C.G. Sodini, P. Ko, J. Moll, “The effect of high fields on MOS device and circuit performance,” IEEE transactions on Electron Devices, October 1984, pp [4] J. M. Rabaey, A. Chandrakasan, B. Nikolic, “Digital Integrated Circuits,” Second edition, 2003

20 Thank You


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