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10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL.

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Presentation on theme: "10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL."— Presentation transcript:

1 10/28/2009VLSI Design & Test Seminar1 Diagnostic Tests and Full- Response Fault Dictionary Vishwani D. Agrawal ECE Dept., Auburn University Auburn, AL 36849 October 28, 2009

2 10/28/2009VLSI Design & Test Seminar2 A Two Phase Approach for Minimal Diagnostic Test Set Generation Mohammed Ashfaq Shukoor Vishwani D. Agrawal 14th IEEE European Test Symposium Seville, Spain, May 25-28, 2009 Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA

3 10/28/2009VLSI Design & Test Seminar3 A Primal-Dual Solution to Minimal Test Generation Problem Auburn University, Department of Electrical and Computer Engineering Auburn, AL 36849, USA Mohammed Ashfaq Shukoor Vishwani D. Agrawal 12 th IEEE VLSI Design and Test Symposium, 2008, Bangalore

4 10/28/2009VLSI Design & Test Seminar44 Outline  Introduction  Motivation  Fault Diagnostic Table  Diagnostic ILP  Diagnostic Fault Independence  2-phase Approach  Results  Conclusion & Future Work

5 10/28/2009VLSI Design & Test Seminar55 Fault Dictionary Based Diagnosis Fault dictionary is a database of simulated test responses for all modeled faults. Used by some diagnosis algorithms: –It is fast –No simulation at the time of diagnosis. Dictionary can be very large, however! Two most popular forms of dictionaries are: –Pass-Fail Dictionary –Full-Response Dictionary

6 10/28/2009VLSI Design & Test Seminar66 Pass-Fail Dictionary For each vector store the list of all detectable faults. Total storage requirement: F  T bits, where F is number of faults and T is number of vectors. Faults Test Vectors t1t2t3t4t5 f1 f2 f3 f4 f5 f6 f7 f8 1001111110011111 0111001001110010 1111000111110001 0101100001011000 0110000101100001 Example: Fault Syndrome (Signature) ‘1’ → detected (fail) ‘0’ → not detected (pass)

7 10/28/2009VLSI Design & Test Seminar77 Full-Response Dictionary Faults Output Responses t1t2t3t4t5 f1 f2 f3 f4 f5 f6 f7 f8 1 0 1 0 1 0 1 0 1 0 1 1 0 0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0 0 1 0 1 0 1 0 ‘1’ → detected ‘0’ → not detected Fault Syndrome For each vector, store the fault detection data for all outputs. Total storage requirement: F  T  O bits, where F is number of faults, T is number of vectors and O is number of outputs. Example: 2 outputs

8 10/28/2009VLSI Design & Test Seminar88 Motivation for Diagnostic Test Set Minimization  The amount of data in a full-response dictionary is (F  T  O).  Previous work on dictionary compaction has been concentrated on managing the dictionary organization and encoding.  Data in a full-response dictionary can be optimized by minimizing the number of vectors in the diagnostic test set.

9 10/28/2009VLSI Design & Test Seminar99 Faults Output Responses T1T2T3T4T5 F11 0 0 F21 1 01 0 F30 11 1 00 F40 1 0 0 10 F50 0 10 1 F60 0 10 F71 00 0 10 0 1 F80 1 0 0 Faults Output Responses T1T2T3T4T5 1223000112230001 1110222111102221 F1 F2 F3 F4 F5 F6 F7 F8 0000102000001020 1203000112030001 Fault Diagnostic Table  We compact the full-response dictionary into a diagnostic table, which contains information on detection and distinguishability of faults. Example: Consider a circuit with 2 outputs, having 8 faults that are detected and diagnosed by 5 test vectors Full-response Dictionary Fault Diagnostic Table 1 2 3 0 3 0 1 0

10 10/28/2009VLSI Design & Test Seminar10 Diagnostic ILP Subject to constraints: Objective: minimize integer [0, 1], j = 1, 2,..., Jvjvj i = 1, 2,..., K (2) (4) (1) If v j = 1, then vector j is included in the minimized vector set If v j = 0, then vector j is not included in the minimized vector set K is the number of faults in a combinational circuit J is the number of vectors in the unoptimized vector set coefficient a ij ≥ 1 only if the fault i is detected by vector j, else it is 0 k = 1, 2,..., K-1 p = k+1,..., K (3) Fault number ( k) Vector number ( j ) 1 2 3 4..... J 10 110.....1 21011.....2 31200.....0 42102.....3...................... K0509.....2

11 10/28/2009VLSI Design & Test Seminar11 Independent Faults [1] : Two faults are independent if and only if they cannot be detected by the same test vector. T(f 1 ) T(f 2 ) f 1 and f 2 are independent f 1 and f 2 are not independent T(f 1 ) T(f 2 ) [1] S. B. Akers, C. Joseph, and B. Krishnamurthy, “On the Role of Independent Fault Sets in the Generation of Minimal Test Sets,” Proc. International Test Conf., 1987, pp. 1100–1107. Generalized Fault Independence (Vector-Specific, Multiple- Outputs): A pair of faults detectable by a vector set V is said to be independent with respect to vector set V, if there is no single vector that detects both faults and produces an identical output response. Fault Independence

12 10/28/2009VLSI Design & Test Seminar12 Fault detection Table Fault diagnostic Table (a) Fault independence (b) Generalized fault independence Example (Two-Output Circuit) Guaranteed diagnosis

13 10/28/2009VLSI Design & Test Seminar13 Effect of Generalized Independence Relation on the Constraint Set Sizes

14 10/28/2009VLSI Design & Test Seminar14 Phase-1: Use existing ILP minimization technique to obtain a minimal detection test set from the given unoptimized test set. Find the faults not diagnosed by the minimized detection test set. Phase-2: Run the diagnostic ILP on the remaining unoptimized test set to obtain a minimal set of vectors to diagnose the undistinguished faults from Phase-1. Minimal detection test set of Phase-1 Minimal set of diagnostic vectors from Phase-2 Complete diagnostic test set Two-Phase Method

15 10/28/2009VLSI Design & Test Seminar15 Comparison Between 1-Step Diagnostic ILP Run and 2-Phase Method Complete Diagnostic Test Set 4-b ALU c17 c432 c880

16 10/28/2009VLSI Design & Test Seminar16 Results SUN Fire 280R, 900 MHz Dual Core machine ATPG – ATALANTA Fault Simulator – HOPE AMPL Package with CPLEX solver for formulating and solving Linear Programs

17 10/28/2009VLSI Design & Test Seminar17 Circuit No. of faults Phase-1Phase-2 Optimized diagnostic test set Original unoptim. Vectors* Minimal detection tests No. of undiag. faults No. of unoptim. vectors No. of constraints Minimized additional vectors 4b ALU 227270124325830618 c17 22324628326 c432 52020363015320061012151 c499 750705522865310254 c880 942138424172135841733 c1355 1566903841172113112286 c1908 18701479107543137218621128 c2670 2630420070833413038351121 c3540 3291396995761387414627122 c5315 52911295631185123240542105 c6288 77103611624163455341228 c7552741949241221966480219631153 2-Phase Method * M. A. Shukoor, Fault Detection and Diagnostic Test Set Minimization, Master’s thesis, Auburn University, ECE Department, May 2009. * M. A. Shukoor and V. D. Agrawal, “A Primal-Dual Solution to the Minimal Test Generation Problem,” Proc. 12th VLSI Design and Test Symp., 2008, pp. 169–179.

18 10/28/2009VLSI Design & Test Seminar18 Diagnostic Characteristics of Minimized Complete Diagnostic Test Set 1 Circuit 2 Total Vectors 3 No. of Faults 4 Uniquely Diagnosed Faults 5 No. of CEFS 6 Undiag. Faults (3 – 4) 7 No. of Syndromes (4 + 5) 8 Maximum Faults per Syndrome 9 Diagnostic Resolution 4b ALU18227 00 11.000 c17622 00 11.000 c43251520 488163250421.032 c49954750 726122473821.016 c88033942 8325511088721.132 c1355861566 397532116992931.686 c19081271870 1380238490161881.156 c26701212630 20272636032290111.149 c35401223291 2720234571303381.085 c53151055291 4496381795487741.085 c6288287710 569010092020669931.151 c7552153741955988481821644671.151

19 10/28/2009VLSI Design & Test Seminar19 2-Phase vs. Previous Work Circuit Pass-fail dictionary compaction [1] 2-Phase Approach [This work] Fault coverage % Minimized vectors Undisting. fault Pairs CPU s Fault coverage % Minimized vectors Undisting. Fault Pairs CPU s c43297.5268930.198.6654150.94 c499----98.9554120.39 c88097.52631040.297.5642642.56 c135598.57888780.898.60807660.34 c190894.1213912082.195.691013990.49 c267084.407918382.884.24694498.45 c354094.49205158510.694.5213559017.26 c531598.83188157915.498.6212347225.03 c628899.56374491165999.56171013337.89 c755291.97198443833.892.32128128918.57 [1] Y. Higami and K. K. Saluja and H. Takahashi and S. Kobayashi and Y. Takamatsu, “Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits,” Proc. ASPDAC, 2006, pp. 75-80.

20 10/28/2009VLSI Design & Test Seminar20 Conclusion Minimization of a diagnostic test set is carried out without loss of diagnostic resolution of a full-response dictionary. We have formulated the diagnostic ILP which is an exact method to minimize a diagnostic test set. The newly defined generalized independence relation between pairs of faults reduces the number of fault-pairs that needs to be distinguished. The two-phase approach has polynomial time complexity (in empirical sense) and is effective in producing compact diagnostic test sets. New problems to be solved: –Define a diagnostic coverage metric similar to the stuck-at detection coverage. –Develop ATPG algorithms to find a distinguishing test for a pair of faults.

21 10/28/2009VLSI Design & Test Seminar21 Thank you …

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