Presentation on theme: "Sp09 CMPEN 411 L16 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 16: Introduction to Soft Errors [Adapted from Rabaey’s Digital Integrated Circuits,"— Presentation transcript:
Sp09 CMPEN 411 L16 S.2 What is Soft Error Soft errors are circuit errors caused due to excess charge carriers induced primarily by external radiations These errors cause an upset event but the circuit it self is not damaged. Same a SEU (single event upset)
Sp09 CMPEN 411 L16 S.3 B p substrate G n+ n channel Soft Errors l The Phenomena + - A particle strike Current
Sp09 CMPEN 411 L16 S.4 Soft Errors l The Phenomena V DD V out CLCL V in A particle strike Bit Flip !!! A particle strike !B L BLBL WLWL 0->1 1->0 0
Sp09 CMPEN 411 L16 S.5 What cause Soft Errors? At ground level, there are three major contributors to Soft errors. 1. Cosmic Ray induced neutrons 2. Alpha particles emitted by decaying radioactive impurities in packaging or interconnect materials. 3. Neutron induced 10 B fission which releases a Alpha particle and 7 Li
Sp09 CMPEN 411 L16 S.6 Evidence of Cosmic Ray Strikes Documented strikes in large servers found in error logs l Normand, “Single Event Upset at Ground Level,” IEEE Transactions on Nuclear Science, Vol. 43, No. 6, December Sun Microsystems, 2000 l Cosmic ray strikes on L2 cache with no error detection or correction -caused Sun’s flagship servers to suddenly and mysteriously crash! l Companies affected -Baby Bell (Atlanta), America Online, Ebay, & dozens of other corporations -Verisign moved to IBM Unix servers (for the most part)
Sp09 CMPEN 411 L16 S.7 Reactions from Companies Fujitsu SPARC in 130 nm technology l 80% of 200k latches protected with parity l compare with very few latches protected in Mckinley l ISSCC, 2003 IBM declared 1000 years system MTBF as product goal l very hard to achieve this goal in a cost-effective way
Sp09 CMPEN 411 L16 S.8 Soft Error Rate (SER) N flux : intensity of the neutron flux. CS : the area of the cross section of the node. Q critical : critical charge necessary for a bit flip. Q s : the charge collection efficiency.
Sp09 CMPEN 411 L16 S.9 Soft Errors For a soft error to occur at a specific node in a circuit, the collected charge Q at that particular node should be more than Q critical. Q critical is proportional to the node capacitance and the supply voltage. Q s is dependent on doping. As CMOS device sizes decrease, the charge stored at each node decreases (due to lower nodal capacitance and lower supply voltages).
Sp09 CMPEN 411 L16 S.10 Modeling of a particle strike
Sp09 CMPEN 411 L16 S.11 A SPICE simulation for SRAM A particle strike !BL BL WL 0->1 1->0 0
Sp09 CMPEN 411 L16 S.12 Qcrit as a function of Vdd and Litho Wissel, IBM CICC 2003
Sp09 CMPEN 411 L16 S.13 Problems caused by SEU Soft Errors can cause problems in different ways l Change the data value in the Caches and Memory l Corrupt the execution of instruction due the flip of data in the pipeline registers. l Change the character of a SRAM-Based FGPA circuit. (Firm Error) l Datapath logic SET (Single Event Transient) caught by registers/memory
Sp09 CMPEN 411 L16 S.14 SEU in memory A particle strike !B L BL WL 0->1 1->0 0 When Memories Forget!
Sp09 CMPEN 411 L16 S.16 SEU in FPGA source: actel
Sp09 CMPEN 411 L16 S.17 SEU in FPGA: routing GRM: General Routing Matrix
Sp09 CMPEN 411 L16 S.18 SEU in FPGA: function Source: Semico 2002Source: Semico 2002
Sp09 CMPEN 411 L16 S.19 SEU in logic: Bit flips caught by FF or memory
Sp09 CMPEN 411 L16 S.20 Error Masking in logic Logical masking : A particle strikes a portion of the combinational logic that doesn’t determine output. Electrical masking : The pulse resulting from a particle strike is attenuated by subsequent logic gates. Latching-window masking : The pulse resulting from a particle strike reaches a latch, but not at the clock transition.
Sp09 CMPEN 411 L16 S.22 SEU in logic: Errors Due to Data SETs Source: K. Bernstein, IBM
Sp09 CMPEN 411 L16 S.23 SEU in logic: Errors Due to Data SETs Clock Data Setup TimeHold Time Non-Latching SEU Earliest-Latching SEU Non-Latching SEU Latest-Latching SEU Window of Vulnerability
Sp09 CMPEN 411 L16 S.24 Impact of technology scaling on SER Source: H.Stork, CTO of TI, IRPS 2004
Sp09 CMPEN 411 L16 S.25
Sp09 CMPEN 411 L16 S.26 Physical Solutions are hard Shielding? l No practical absorbent (e.g., approximately > 10 ft of concrete) Radiation-hardened cells? l 10x improvement possible with significant penalty in performance, area, cost l 2-4x improvement may be possible with less penalty
Sp09 CMPEN 411 L16 S.28 Increase the capacitance Tarnik et al. Intel 2002 CK D CK# Q GND VDD capacitor
Sp09 CMPEN 411 L16 S.29 ST tames soft errors in SRAM by adding capacitors ST tames soft errors in SRAM by adding capacitors By Ron Wilson, EE Times January 13, 2004 (4:42 a.m. EST) URL: increased the node capacitance of an SRAM cell substantially with only about a 5 percent area increase with only about a 5 percent area increase with a 250X improvement on SER
Sp09 CMPEN 411 L16 S.30 Space redundancy: Redundant Logic Logic 1 Logic 2 Voter Logic3 Point of failure!!
Sp09 CMPEN 411 L16 S.31 Temporal Sampling Latch with Internal Clock Delays DFF DQ CLOCK OUT MAJ 2ΔT2ΔT IN ΔTΔT DFF DQ DQ Asynchronous VotingTemporal Sampling
Sp09 CMPEN 411 L16 S.32 A fast way to check your FIT rate IROC just release a web-based SER estimation tool
Sp09 CMPEN 411 L16 S.33 Next Lecture Next lecture l Dynamic logic -Reading assignment – Rabaey, et al, Ch 7