1. Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing
21st October 2010
Soft Errors Hardening Techniques in Nanometer SRAM Memories Author: Gabriel Torrens Caldentey Thesis Advisors: Sebastià Bota Ferragut, Ph.D. Jaume Segura Fuster, Ph.D. Universitat de les Illes Balears (UIB)

2. Introduction. Soft Errors
Soft errors caused by ionizing particles are becoming a major concern in CMOS SRAMs
Soft errors generate non-destructive effects
Non permanent damage
Information loss
Reverse the state of an SRAM cell: Single Event Upset (SEU)
When the Soft Error Rate of a design is to be reduced, memories are the first priority:
Memories are more sensitive to Soft Errors than logic
Designed to reach the highest density
Memories are usually the largest parts of modern designs

3. Introduction. Radiation Impact on SRAMs
If a sensitive node is in the proximity of the ionizing track of a particle
It collects part of the generated charge producing a transient current pulse at the node
Qcrit is the parameter usually used to evaluate the hardness of an SRAM
The minimum charge collected by a node that makes the cell flip
We developed an iterative method based on electrical simulations
Focus on 65nm CMOS 6T SRAMs
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4. Introduction Parameter variations, one of the most challenging issues
In 6T SRAMs the so-called wide-cell layouts showed to be more reliable
All poly lines placed in the same direction
Parameter variations can be further reduced
Layouts without bends in diffusion regions
These layouts are incompatible with most of the existing SRAM hardening techniques
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5. SRAM Hardening Techniques & Future Work
SRAM hardening techniques in hold mode
Selection of Vt
Transistor width modulation
SRAM behavior in read mode
Word-line voltage modulation hardening technique
Future work
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6. Hardening techniques in hold mode
Threshold voltage selection
Nanometer CMOS technologies provide different Vt
Exploit this multi-Vt environment to construct SRAM cells with different combinations of Vt
All combinations tested
Differences barely exceed a few percent
Not an efficient procedure: it may be reserved to adjust the speed leakage ratio with a marginal effect on Qcrit
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7. Hardening techniques in hold mode
Transistor Width Modulation
Wide-layout with straight diffusions regions
Transistor modulation that does not introduce bends
2 constraints:
2 degrees of freedom (n, p)
Wn=n·Wmin Wp=p·Wmin
The wider the transistors are, the more robust the cell becomes
The slope is greater in the p axis:
More efficient to increase only pMOS
Transistor width increase has a negative impact in area:
A tradeoff must be established
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8. SRAM behavior in read mode
A cell reaches its weakest state (in terms of SNM) when it is in read mode
We computed the Qcrit in a sequence of HOLD, READ, HOLD modes
In read mode results of transistor width modulation are in line with the previously described
A specific strategy can be implemented for read mode:
Word-line voltage modulation: Decrease WL Voltage
The cell undergoes a significant Qcrit reduction when it is read
A cell is weakened from a point of view of:
SNM
Qcrit
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9. Hardening techniques in read mode
Qcrit and SNM representation against WL voltage:
Reducing the WL voltage has a negative impact in read time
Only moderate reductions are practical
WL reduced to 83% of nominal value
Qcrit increases 16% % read time penalty
Implementation
Only modification of the last stage of the row decoder
Only affects read mode. Write mode performed as usual
As the WL voltage drops below its nominal value, the Qcrit begins to rise until it reaches the value for HOLD
The same behavior is observed for SNM
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10. Future work We are currently designing a complete 65 nm SRAM memory
Objectives:
Characterize the behavior of a real device
Test the effectiveness of some of the previously described techniques
The memory will include cells of different sizes and implement a WL modulation strategy
The memory will include 8T cells
Show better read stability and read robustness. Dedicated read port
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11. Thank you for your attention!
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