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Soft Errors Hardening Techniques in Nanometer SRAM Memories Author: Gabriel Torrens Caldentey Thesis Advisors:Sebastià Bota Ferragut, Ph.D. Jaume Segura.

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Presentation on theme: "Soft Errors Hardening Techniques in Nanometer SRAM Memories Author: Gabriel Torrens Caldentey Thesis Advisors:Sebastià Bota Ferragut, Ph.D. Jaume Segura."— Presentation transcript:

1 Soft Errors Hardening Techniques in Nanometer SRAM Memories Author: Gabriel Torrens Caldentey Thesis Advisors:Sebastià Bota Ferragut, Ph.D. Jaume Segura Fuster, Ph.D. Universitat de les Illes Balears (UIB) Barcelona Forum on Ph.D. Research in Communications, Electronics and Signal Processing 21 st October 2010

2 Introduction. Soft Errors Soft errors caused by ionizing particles are becoming a major concern in CMOS SRAMs Soft errors generate non-destructive effects –Non permanent damage –Information loss Reverse the state of an SRAM cell: Single Event Upset (SEU) When the Soft Error Rate of a design is to be reduced, memories are the first priority: –Memories are more sensitive to Soft Errors than logic Designed to reach the highest density –Memories are usually the largest parts of modern designs Barcelona Forum on Ph.D. Research in Electronic Engineering 2

3 Introduction. Radiation Impact on SRAMs If a sensitive node is in the proximity of the ionizing track of a particle –It collects part of the generated charge producing a transient current pulse at the node Q crit is the parameter usually used to evaluate the hardness of an SRAM –The minimum charge collected by a node that makes the cell flip We developed an iterative method based on electrical simulations Focus on 65nm CMOS 6T SRAMs Barcelona Forum on Ph.D. Research in Electronic Engineering 3

4 Introduction Parameter variations, one of the most challenging issues –In 6T SRAMs the so-called wide-cell layouts showed to be more reliable All poly lines placed in the same direction –Parameter variations can be further reduced Layouts without bends in diffusion regions –These layouts are incompatible with most of the existing SRAM hardening techniques Barcelona Forum on Ph.D. Research in Electronic Engineering 4

5 SRAM Hardening Techniques & Future Work SRAM hardening techniques in hold mode –Selection of Vt –Transistor width modulation SRAM behavior in read mode –Word-line voltage modulation hardening technique Future work Barcelona Forum on Ph.D. Research in Electronic Engineering 5

6 Hardening techniques in hold mode Threshold voltage selection –Nanometer CMOS technologies provide different Vt –Exploit this multi-Vt environment to construct SRAM cells with different combinations of Vt –All combinations tested Differences barely exceed a few percent Not an efficient procedure: it may be reserved to adjust the speed leakage ratio with a marginal effect on Q crit Barcelona Forum on Ph.D. Research in Electronic Engineering 6

7 Hardening techniques in hold mode Transistor Width Modulation –Wide-layout with straight diffusions regions Transistor modulation that does not introduce bends –2 constraints: –2 degrees of freedom ( n, p ) Barcelona Forum on Ph.D. Research in Electronic Engineering 7 W n = n · W min W p = p · W min The wider the transistors are, the more robust the cell becomes The slope is greater in the p axis: More efficient to increase only pMOS Transistor width increase has a negative impact in area: A tradeoff must be established

8 SRAM behavior in read mode A cell reaches its weakest state (in terms of SNM) when it is in read mode We computed the Q crit in a sequence of HOLD, READ, HOLD modes In read mode results of transistor width modulation are in line with the previously described A specific strategy can be implemented for read mode: –Word-line voltage modulation: Decrease WL Voltage Barcelona Forum on Ph.D. Research in Electronic Engineering 8 The cell undergoes a significant Q crit reduction when it is read A cell is weakened from a point of view of: SNM Q crit

9 Hardening techniques in read mode Q crit and SNM representation against WL voltage: Reducing the WL voltage has a negative impact in read time –Only moderate reductions are practical –WL reduced to 83% of nominal value Q crit increases 16% 5% read time penalty Implementation –Only modification of the last stage of the row decoder –Only affects read mode. Write mode performed as usual Barcelona Forum on Ph.D. Research in Electronic Engineering 9 As the WL voltage drops below its nominal value, the Q crit begins to rise until it reaches the value for HOLD The same behavior is observed for SNM

10 Future work We are currently designing a complete 65 nm SRAM memory Objectives: –Characterize the behavior of a real device –Test the effectiveness of some of the previously described techniques The memory will include cells of different sizes and implement a WL modulation strategy –The memory will include 8T cells Show better read stability and read robustness. Dedicated read port Barcelona Forum on Ph.D. Research in Electronic Engineering 10

11 Thank you for your attention! Barcelona Forum on Ph.D. Research in Electronic Engineering__


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