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IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany © All rights reserved An Implementation Study on Fault Tolerant LEON-3 Processor System Z. Stamenković
IHP Innovations for High Performance MicroelectronicsSlide 2© All rights reserved Outline Radiation and fault tolerance System description Implementation details Test results Under way
IHP Innovations for High Performance MicroelectronicsSlide 3© All rights reserved Reliability Issues in Radiation Environments Single-event upset (SEU) A change of state caused by a charged particle strike to a sensitive volume in a microelectronic device Alpha particles (helium-4 nuclei) emitted by radioactive atoms found in packaging materials Thermal neutrons in certain device materials that are heavily doped with 10 B High-energy terrestrial cosmic rays (play a major role) SEU-induced latch-up A failure mechanism of CMOS integrated circuits characterized by excessive current due to parasitic PNPN paths
IHP Innovations for High Performance MicroelectronicsSlide 4© All rights reserved Fault Tolerance of LEON-3 Processor SEU tolerance by design (Gaisler Research) Triple-module-redundancy (TMR) on all flip-flops Three copies of a flip-flop Two of three voting on output Register file error-correction (up to 4 errors per 32-bit word) Cache RAM error-correction (up to 4 errors per tag or 32-bit word) Autonomous and software transparent error handling No timing impact due to error detection or correction Fault-tolerant memory controller Provides an Error Detection And Correction Unit (EDAC) Corrects one and detects two errors Not immune to SEU-induced latch-up (in present IHP technology)
IHP Innovations for High Performance MicroelectronicsSlide 5© All rights reserved LEON-3 Processor System LEON_3FT Core 8 Reg. Windows LEON_3FT Core 8 Reg. Windows FT Memory Controller FT Memory Controller 8 x GPIO GPIOEJTAG 2 kByte I- Cache 2 kByte I- Cache 2 kByte D- Cache 2 kByte D- Cache AHB APB 1 x 24bit Timer UART 0 EDAC SRAM FLASH Serial 0 Serial 1 UART 1 Bridge Scan Test FT Add-on Scan-I/F
IHP Innovations for High Performance MicroelectronicsSlide 6© All rights reserved Installation of the release Adaptation of the configuration tool (to include IHPs library) Implementation of data and instruction caches Logic synthesis of the design Implementation of scan chain Generation of the chip layout Simulation (functional, post-synthesis and post-layout net-list) Scan test vectors generation (ATPG) Scan test simulation Adaptation of testbenches EVCD test vectors generation Test specification Documentation Implementation Details
IHP Innovations for High Performance MicroelectronicsSlide 7© All rights reserved Chip Features
IHP Innovations for High Performance MicroelectronicsSlide 8© All rights reserved Test System (Gaisler Research) Target hardware consists of a small mezzanine with Fault Tolerant LEON-3 device mounted on a development board (Pender Electronic Design) Board communicates with a host system (a laptop PC) over one of the on-chip UARTs
IHP Innovations for High Performance MicroelectronicsSlide 9© All rights reserved Test Execution (Gaisler Research) Heavy-ion-error injection Chamber with the vacuum of mbar Californium (Cf-252) source Flux of 25 particles/s/cm 2 at the device surface for 3 hours Paranoia program makes a large number of calculations and registers any computational error or anomaly On-chip monitoring logic reported 281 effective SEU errors, of which 99% were corrected Cross-section for a memory RAM bit was measured to 7.2x10 -8 cm 2
IHP Innovations for High Performance MicroelectronicsSlide 10© All rights reserved Under Way Protection against SEU-induced latch-up
IHP Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt (Oder) Germany ©
CHATELAIN Charly Oral Presentation For B2 Level. Presentation Outline The development of LEON1, LEON2 & LEON3 LEON3 and GRLIB overview Fault Injection.
GaislerMAPLD 2005/ FPGA Design Using the LEON3 Fault Tolerant Processor Core Jiri Gaisler and Sandi Habinc.
ICAP CONTROLLER FOR HIGH-RELIABLE INTERNAL SCRUBBING Quinn Martin Steven Fingulin.
International Graduate School Cottbus / IHP microelectronics Im Technologiepark Frankfurt (Oder) Germany IHP Im Technologiepark Frankfurt.
Discussion of: “Terrestrial-based Radiation Upsets: A Cautionary Tale” CprE 583 Tony Kuker 12/06/05.
SiLab presentation on Reliable Computing Combinational Logic Soft Error Analysis and Protection Ali Ahmadi May 2008.
Microprocessor Reliability Robert Pawlowski ECE 570 – 2/19/
FT-UNSHADES Analysis of SEU effects in Digital Designs for Space Gioacchino Giovanni Lucia TEC-EDM, MPD - 8 th March Phone: +31.
April 30, Cost efficient soft-error protection for ASICs Tuvia Liran; Ramon Chips Ltd.
Xilinx V4 Single Event Effects (SEE) High-Speed Testing Melanie D. Berg/MEI – Principal Investigator Hak Kim, Mark Friendlich/MEI.
Single Event Effects in microelectronic circuits Author: Klemen Koselj Advisor: Prof. Dr. Peter Križan.
Giuseppe De Robertis - INFN Sez. di Bari 1 SEU – SET test structures.
Z. Stamenković 1, M. Giles 2, and F. Russi 2 1 IHP GmbH, Frankfurt (Oder), GERMANY 2 Synopsys Inc., Mountain View, CA, USA 13th IEEE European Test Symposium,
Baloch 1MAPLD 2005/1024-L Design of a ‘Single Event Effect’ Mitigation Technique for Reconfigurable Architectures SAJID BALOCH Prof. Dr. T. Arslan 1,2.
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March 16-18, 2008SSST'20081 Soft Error Rate Determination for Nanometer CMOS VLSI Circuits Fan Wang Vishwani D. Agrawal Department of Electrical and Computer.
M. Adinolfi – University of Oxford – MAPMT Workshop – Imperial College 27 June Rad-Hard qualification for the LHCb RICH L0 electronics M. Adinolfi.
10 December 2012 Clive Max Maxfield All Programmable FPGAs, SoCs, and 3D ICs Part V. Advanced Concepts and Future Trends 1.
1 A Design Approach for Radiation-hard Digital Electronics Rajesh Garg Nikhil Jayakumar Sunil P Khatri Gwan Choi Department of Electrical and Computer.
Architectural Optimizations Ed Carlisle. DARA: A LOW-COST RELIABLE ARCHITECTURE BASED ON UNHARDENED DEVICES AND ITS CASE STUDY OF RADIATION STRESS TEST.
Scrubbing Approaches for Kintex-7 FPGAs Michael Wirthlin Brigham Young University, CHREC Provo, Utah, USA.
SHIELD The VLSI Systems Center - BGU 1 SEU Hardening Incorporating Extreme Low Power Bitcell Design (SHIELD) Ariel Pescovsky and Oron Chertkow Supervisors:
Single Event Upsets (SEUs) – Soft Errors By: Rajesh Garg Sunil P. Khatri Department of Electrical and Computer Engineering, Texas A&M University, College.
1 Dependability Benchmarking of VLSI Circuits Cristian Constantinescu Intel Corporation.
Circuit Modeling and Fault Injection Approach to Predict SEU Rate and MTTF in Complex Circuits Fabian Vargas, Alexandre Amory Catholic.
1 Fault Tolerant FPGA Co-processing Toolkit Oral defense in partial fulfillment of the requirements for the degree of Master of Science 2006 Oral defense.
ATMEL ATF280E Rad Hard SRAM Based FPGA SEE test results Application oriented SEU Sensitiveness Bernard BANCELIN ATMEL Nantes SAS, Aerospace Business Unit.
Embedded Systems Laboratory Informatics Institute Federal University of Rio Grande do Sul Porto Alegre – RS – Brazil SRC TechCon 2005 Portland, Oregon,
Sp09 CMPEN 411 L16 S.1 CMPEN 411 VLSI Digital Circuits Spring 2009 Lecture 16: Introduction to Soft Errors [Adapted from Rabaey’s Digital Integrated Circuits,
Gill 1 MAPLD 2005/234 Analysis and Reduction Soft Delay Errors in CMOS Circuits Balkaran Gill, Chris Papachristou, and Francis Wolff Department of Electrical.
Sana Rezgui 1, Jeffrey George 2, Gary Swift 3, Kevin Somervill 4, Carl Carmichael 1 and Gregory Allen 3, SEU Mitigation of a Soft Embedded Processor in.
1-1 Embedded Software Development Tools and Processes Hardware & Software Hardware – Host development system Software – Compilers, simulators etc. Target.
Synthesis Of Fault Tolerant Circuits For FSMs & RAMs Rajiv Garg Pradish Mathews Darren Zacher.
Radiation Effects on FPGA and Mitigation Strategies Bin Gui Experimental High Energy Physics Group 1Journal Club4/26/2015.
Spring 07, Apr 17, 19 ELEC 7770: Advanced VLSI Design (Agrawal) 1 ELEC 7770 Advanced VLSI Design Spring 2007 Soft Errors and Fault-Tolerant Design Vishwani.
Chapter 6 Computing Components Discovering Computers 2016 Tools, Apps, Devices, and the Impact of Technology.
Complex Upset Mitigation Applied to a Re-Configurable Embedded Processor EEL 6935 Lu Hao Wenqian Wu.
SEU WK summary. Technology comparison Sandro Bonacini - PH/ESE nm seems to saturate at a cross-section 3.4× less than 130nm.
Wang-110 D/MAPLD SEU Mitigation Techniques for Xilinx Virtex-II Pro FPGA Mandy M. Wang JPL R&TD Mobility Avionics.
MURI Neutron-Induced Multiple-Bit Upset Alan D. Tipton 1, Jonathan A. Pellish 1, Patrick R. Fleming 1, Ronald D. Schrimpf.
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VirtexIIPRO FPGA Device Functional Testing In Space environment. Performed by: Mati Musry, Yahav Bar Yosef Instuctor: Inna Rivkin Semester: Winter/Spring.
1 The NSEU Sensitivity of Static Latch Based FPGAs and Flash Storage CPLDs Joseph Fabula Jason Moore Austin Lesea Saar Drimer MAPLD2004 This work has benefited.
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